Abstract: A memory having a SRAM, a DRAM, and two independent and functionally identical IO ports. Each port may be used as a read-only, a write-only, or a read-write port. One port may perform a read access to the SRAM, whereas the other port may carry out a write access to the SRAM in the same clock cycle. Each and every location of the SRAM may be accessed from any of the ports. Each port comprises a two-stage pipelined data path for providing a read or write access to the SRAM. Stage 1 decodes control and write enable signals, latches address signals and performs the output of read data. Stage 2 supports accesses to SRAM cells for writing and reading data. In a unified-port mode of operation, two 16-bit ports may be combined to produce a single port supporting a 32-bit write or read access to the SRAM. In a data burst mode of operation, each port may be programmed to select individual length of data bursts and individual burst type.

Abstract: A multi-port RAM (MPRAM) having a SRAM and a DRAM on a single chip. Separate pins are provided on the chip to supply independent chip select signals for the SRAM and the DRAM. When the SRAM chip select signal is at a high level, a clock generator is prevented from producing an internal clock signal for the SRAM. As a result, no SRAM operation is performed in response to a SRAM command. Similarly, when the DRAM chip select signal is high, a clock generator produces no internal clock signal for the DRAM. As a result, DRAM operations are prevented from being performed in response to DRAM commands.

Abstract: A multi-port RAM (MPRAM) having a SRAM and a DRAM. A global bus is arranged between the DRAM and the SRAM to provide bi-directional transfer of 256-bit data blocks between the SRAM and the DRAM. Two independent input/output ports are coupled to the SRAM to enable a user to write or read data to or from the SRAM and DRAM. Byte masking is provided for each of the ports to mask bytes of data supplied to the MPRAM. A write-per-bit (WPB) mask register is arranged between the ports and the SRAM to prevent unnecessary bits of input data from being written into the SRAM. A byte write enable (BWE) mask register is arranged between the SRAM and the DRAM to prevent unnecessary bytes of data from being transferred from the SRAM to the DRAM. Each of the mask registers may be loaded with mask data from both of the ports concurrently, or from any one of them.

Abstract: A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.

Abstract: A memory having a SRAM, a DRAM and two external IO ports is provided. The SRAM has three IO ports for enabling the external IO ports and the DRAM to access each and every memory cell in the DRAM. Each SRAM cell is provided with two IO ports coupled to the external IO ports, and with an IO port for transferring data to and from the DRAM. The triple-port SRAM cell comprises three input data lines coupled to a latching circuit for writing data supplied from the external IO ports and the DRAM, and three output data lines coupled to the latching system for reading stored data to the external IO ports and the DRAM. Three write address lines and three read address lines provide addressing of the SRAM cell for data writing and reading operations performed by the external IO ports and the DRAM. Each SRAM cell may be read concurrently via all three ports to make the most current data stored in the SRAM accessible from any port at any time.