Abstract: An electronic device provides, to a display, data to present a user interface that includes a plurality of user interface objects, and a current focus on a first user interface object. While the display is presenting the user interface, the electronic device receives an input that corresponds to a movement of a contact across on a touch-sensitive surface. The electronic device, in response to receiving the input and in accordance with a determination that a first axis is a dominant axis, moves the current focus along the first axis by a first amount and along the second axis by a second amount. The amount of movement of the current focus along the second axis is reduced to a first non-zero amount by a scaling factor that is based on one or more inputs received prior to receiving the input.

Abstract: Electrodes are positioned substantially in contact with at least one surface of a solid to generate or absorb alkali metals when a voltage is applied between the electrodes.

Abstract: Electrodes are positioned substantially in contact with at least one surface of a solid to generate or absorb alkali metals when a voltage is applied between the electrodes.

Abstract: Method and apparatus for high field asymmetric waveform ion mobility spectrometry in an electronic chip assembly, including an input section, an ion filter and detection section and a control section, in which ion filtering proceeds in a planar chamber under influence of high field asymmetric periodic signals, with detection integrated into the flow path, for producing accurate, real-time, data for identification of a broad range of chemical compounds.

Abstract: Method and apparatus for high field asymmetric waveform ion mobility spectrometry in an electronic chip assembly,, including an input section, an ion filter and detection section and a control section, in which ion filtering proceeds in a planar chamber under influence of high field asymmetric periodic signals, with detection integrated into the flow path, for producing accurate, real-time, data for identification of a broad range of chemical compounds.

Abstract: A method of processing a substrate includes depositing a glass bonding layer on a first surface of one of either a substrate or a handle wafer, positioning the handle wafer in contact with the substrate via the bonding layer, and heating the substrate, bonding layer, and handle wafer at a temperature below about 425° C. to bond the handle wafer to the substrate. The bonding layer adjoining the substrate and handle wafer is formed of a non-silicate glass that is substantially unsusceptible to outgassing in ultrahigh vacuum environments and is impervious to substantial chemical and structural degradation during thermal processing at temperatures at least up to about 500° C.

Abstract: An integrated circuit (IC) header subassembly includes a spacer mounted to the header. The IC die assembly, consisting of an IC die or IC die carrier assembly, is mounted to spacer which is mounted to the header. The coefficient of thermal expansion of the spacer is selected to be between the coefficient of thermal expansion of the IC die assembly and the header minimize stresses due to thermal expansion and contraction. In addition, the spacer is substantially smaller in width and length and the IC die assembly and the header whereby the IC die assembly appears to be pedestal mounted. By minimizing the length of the contacting surfaces between the spacer and the IC die assembly, the risk of warping or cracking due to differences in thermal expansion can be reduced. This allows for much larger IC dies and pixel arrays to be used.

Abstract: An integrated circuit (IC) die carrier assembly includes a thinned IC die mounted to a substrate or carrier. The IC die is mounted to the carrier via a thin layer of glass. The carrier facilitates fixturing and provides support during the lapping process used to thin the die. Ball bonding, wire bonding, thin film or thick film conductors can be used to interconnect the pads on the IC die to the pads on the carrier. The coefficients of the thermal expansion of the IC die and the carrier are closely matched to avoid damage to the IC die due to uneven expansion of the thinned IC die relative to the carrier. The IC die carrier assembly is better suited for ultrahigh vacuum and high temperature environments than conventional IC die carrier assemblies.

Abstract: An integrated circuit (IC) die carrier assembly includes a thinned IC die mounted to a substrate or carrier. The IC die is mounted to the carrier via a thin layer of glass. The carrier facilitates fixturing and provides support during the lapping process used to thin the die. Ball bonding, wire bonding, thin film or thick film conductors can be used to interconnect the pads on the IC die to the pads on the carrier. The coefficients of the thermal expansion of the IC die and the carrier are closely matched to avoid damage to the IC die due to uneven expansion of the thinned IC die relative to the carrier. The IC die carrier assembly is better suited for ultrahigh vacuum and high temperature environments than conventional IC die carrier assemblies.

Abstract: An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceramic package base characterized by a dielectric constant less than 6, of reaction bonded silicon nitride, or a heat spreader material. An electrical conductor is positioned on, embedded in, or attached to the package base for making electrical contact to an electronic device supported on the base and in preferred embodiments, a resistor is attached to the package base. The invention also provides package sidewalls connected to the package base, preferably of reaction bonded silicon nitride, and at least one electrical conductor extending to an outside surface of the package sidewalls for making electrical contact to an electronic device supported by the package base.

Abstract: A method of producing electronic device packages is provided, consisting of the steps of shaping a package preform and heating the package preform in a nitrogen-containing atmoshpere to nitride the package preform. The shaped package preform may consist of package base, sidewall, conductor, resistor, or capacitor components. The package base and sidewall components may be formed of silicon powder. The method also accommodates the step of inserting a semiconducting material into the package preform and heating the semiconducting material component along with the package preform. The inserted semiconducting material component may be processed to define active electronic device areas on the component either before or after the step of heating the shaped package preform and inserted semiconducting material component.

Abstract: The present invention provides an antenna including a relatively thin substantially planar electrically conductive first layer substantially lying in a first plane, and a relatively thin substantially planar electrically conductive second layer substantially lying in a second plane. The first and second layers are disposed such that the first and second planes are substantially parallel and such that they are separated by a distance d. The second layer is smaller than and overlies the first layer and defines a first region extending between the second layer and a portion of the first layer underlying the second layer. The antenna further includes a first dielectric medium having a relatively high dielectric constant and disposed in the first region, and a second dielectric medium having a relatively low dielectric constant and disposed in a second region extending between the first layer and portions of the second plane overlying the first layer and excluding the first region.

Abstract: The present invention provides a miniaturized multilayer microstrip antenna that includes a stack of antenna sub-stacks, a ground element, and a plurality of electrically conductive segments. Each of the antenna sub-stacks includes a pair of substantially parallel outer principal faces. A sandwich of two relatively thin electrically non-conductive substrate elements, separated by a relatively thin electrically conductive layer, extends between each pair of parallel outer principal faces. The electrically conductive layer has at least one void region through which an electrically conductive feedthrough element extends. The feedthrough element also extends between the outer principal faces. The ground element electrically couples the conductive layers of each of the antenna sub-stacks.

Abstract: A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.

Abstract: A viad chip resistor made from an insulative wafer and having a via formed near end of the wafer. Conductive pads surround the vias on both sides of the wafer. A resistive element is formed on one side of the wafer between the vias and is electrically connected to the conductive pads on that side. An array of viad chip resistors, from which said individual viad chip resistors are cut, is also shown.

Abstract: A chip capacitor comprising a plurality of parallel plastic organic film ers which film layers may further include organically bonded ceramic particles, interleaved with multiple thin parallel non-precious metal electrode film layers of aluminum, copper or the like, the capacitor further comprising suitable non-precious metal end caps and connector means the surfaces of adjacent dielectric films and electrodes being bonded together using bonding agents selected to provide the mechanical stability of the film chip capacitor.

Abstract: The invention provides a new apparatus and method for forming thin metal parts of simple or intricate shape and depositing the same onto selected receiving surfaces. The parts may be in the form of wire leads which are bonded to the receiving surfaces. The invention consists in providing a hollow tool which includes a porous body with an exposed surface having a selected two-dimensional or three-dimensional geometry, immersing the surface of the porous body in a melt of a metal which will not wet the surface, pulling the tool away from the metal while applying a suction force to the porous body so that a portion of the melt will adhere to the surface, bringing the tool into contact with a receiving surface, and cooling the surface and removing the suction force so that the adhering portion of the melt will be deposited as a solid or partially solidified body onto the receiving surface.

Abstract: The invention provides a new apparatus and method for forming thin metal parts of simple or intricate shape and depositing the same onto selected receiving surfaces. The parts may be in the form of wire leads which are bonded to the receiving surfaces. The invention consists in providing a hollow tool which includes a porous body with an exposed surface having a selected two-dimensional or three-dimensional geometry, immersing the surface of the porous body in a melt of a metal which will not wet the surface, pulling the tool away from the melt while applying a suction force to the porous body so that a portion of the melt will adhere to the surface, bringing the tool into contact with a receiving surface, and cooling the surface and removing the suction force so that the adhering portion of the melt will be deposited as a solid or partially solidified body onto the receiving surface.