Abstract: A monitor device for selectively detecting and recording conditions at selected points within a system during operation, including a trigger enable memory for storing selectable trigger enabling codes wherein each code corresponds to a trigger signal representing the occurrence of a corresponding condition to be detected, a trigger generation device connected from first selected points and responsive to selected conditions thereupon for generating the trigger signals representing the occurrence of selected conditions, a trigger output device responsive to the enabling codes and the trigger signals for providing trigger outputs upon the occurrence of a trigger signal corresponding to a selected trigger enabling code, and a silo bank memory connected from second selected points and responsive to the trigger outputs for recording conditions present at the second points.

Abstract: A monitoring means for selectively detecting and recording signals representing at selected points within a system, includes trigger generation logic responsive to selected bus signals for generating trigger signals representing the occurrence of selected conditions, and a recording memory for recording the conditions thereupon, a trigger selection logic for selecting trigger outputs corresponding to the trigger signals. The trigger selection logic includes a trigger enabling memory for storing selectable trigger enabling codes, wherein each enabling code corresponds to a trigger signal, and trigger output logic responsive to the trigger enabling codes and to the trigger signals for providing trigger outputs. The trigger enabling codes include bus enabling codes representing selected conditions on a bus of the system, trigger sequence enabling codes corresponding to sequential combinations of trigger signals and external trigger enabling codes corresponding to triggers external to the system.

Abstract: A monitor for selectively detecting and recording conditions at selected points within a system includes a trigger memory for storing patterns of trigger signals, wherein each pattern of trigger signals corresponds to a selected condition to be detected on first points of the system. The trigger memory includes a first port having a read address input connected from the first points and a data output connected to trigger output logic for providing patterns of trigger signals corresponding to the conditions to be detected. Each pattern of trigger signals is stored in the trigger memory location whose address corresponds to a pattern of signals from the first points representing the corresponding condition to be detected. The trigger memory is a dual port memory having a second port with a write address input and a data input for receiving trigger patterns to be stored therein.

Abstract: Any host requesting acccess to the bus must, on its first attempt, wait for N arbitration delay periods after the bus becomes available before attempting to take control of the bus. If another host takes the bus before completion of the arbitration delay period, the host must wait till the next time the bus becomes available. The arbitration delay count is decreased by one for each successive attempt, until the host either gains control of the bus or the aribration delay period goes to zero. At this point it may attempt to take control of the bus as soon as the bus becomes available. If another higher priority host reaches an arbitration delay count of zero during the same arbitration delay count period, the host will be denied and will wait for the next time the bus becomes available, again with an arbitration delay count of zero.