Patents by Inventor William Liu

William Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9646040
    Abstract: Embodiments relate to the implementation of configurable rules that automatically monitor large volumes of data stored in a database. Certain embodiments may leverage the high processing power available to the database engine of an in memory database, in order to perform analysis of large data volumes for compliance and other purposes. Particular embodiments may utilize ABAP Database Connectivity (ADBC) to a HANA in memory database available from SAP AG, in order to implement and execute configurable rules in connection with governance, risk, and compliance (GRC) of large volumes of data stored therein. In various embodiments, an analysis engine in the application layer may rely upon the in memory database engine to execute at least some logic of the configurable rules.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: May 9, 2017
    Assignee: SAP SE
    Inventors: Haiyang Yu, Eric Du, Jiran Ding, Kenny Zhang, Lily Xiao, Tao Feng, Williams Liu, Chris Ge
  • Publication number: 20140279836
    Abstract: Embodiments relate to the implementation of configurable rules that automatically monitor large volumes of data stored in a database. Certain embodiments may leverage the high processing power available to the database engine of an in memory database, in order to perform analysis of large data volumes for compliance and other purposes. Particular embodiments may utilize ABAP Database Connectivity (ADBC) to a HANA in memory database available from SAP AG, in order to implement and execute configurable rules in connection with governance, risk, and compliance (GRC) of large volumes of data stored therein. In various embodiments, an analysis engine in the application layer may rely upon the in memory database engine to execute at least some logic of the configurable rules.
    Type: Application
    Filed: March 19, 2013
    Publication date: September 18, 2014
    Applicant: SAP AG
    Inventors: Haiyang Yu, Eric Du, Jiran Ding, Kenny Zhang, Lily Xiao, Tao Feng, Williams Liu, Chris Ge
  • Publication number: 20070106641
    Abstract: A system and method for determining a quantitative measure of search efficiency of related Web pages. An information goal is specified. A target Web page is identified within a plurality of Web pages. The information goal is searched via a search function in the Web pages to identify potential Web pages that include at least one hyperlink referencing and proximal cues relating to distal content included in another potential Web page. An activation network is formed. A directed graph is built, including nodes corresponding to the potential Web pages and arcs corresponding to the hyperlinks. A weight is assigned to each arc to represent a probability of traversal of the corresponding hyperlink based on a relatedness of keywords in the information goal to the proximal cues. A traversal through the activation network to the node corresponding to the target Web page is evaluated as a quantitative measure of search efficiency.
    Type: Application
    Filed: November 4, 2005
    Publication date: May 10, 2007
    Inventors: Ed Chi, William Liu
  • Publication number: 20070043717
    Abstract: A relevancy association architecture for providing a more effective retrieval of existing product support information in response to client information requests. Product support information for products of a business enterprise is collected and stored in an information library. Relevancy associations are created, based on an ontology such as a context-scenario information organization model, among the product support information stored in the information library and the products provided by the business enterprise. Once the relevancy associations are created, weights are assigned to the associations, wherein the weights designate the certainty of each created relevancy association. When a client requests support for a product of the business enterprise, relevant product support information for the client request is identified based on the relevancy associations. This relevant product support information may then be sent to the requesting client.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Inventors: Paul Arellanes, Mary Burton, Elizabeth Halliday-Reynolds, William Liu, Jason Read, Douglas Yakesch
  • Publication number: 20070043718
    Abstract: A method and system for autonomic relevancy building using information obtained from clients to improve customer support. Upon receiving a client request for product support information, product support information objects representing the requested product support information in an information library are identified. Relevant product support information corresponding to the identified relevant product support information objects are provided to the client. Data regarding whether or not the information provided to the client is relevant may be obtained from the client through implicit feedback (such as, system usage), explicit feedback (such as, user feedback), metadata information, or any combination thereof. Relevancy associations may be created between the product support information objects based on the relevancy data. Relevancy weights may also be assigned to each relevancy association based on the relevancy data, wherein the relevancy weights designate a certainty of each relevancy association.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Inventors: Paul Arellanes, Mary Burton, Elizabeth Halliday-Reynolds, William Liu, Jason Read, Douglas Yakesch
  • Patent number: 7174232
    Abstract: To schedule the release of jobs from a pool of pending jobs, machine information and information about items to be processed are used to determine available machine capacity. Available machine capacity is allocated to jobs subject to multiple job release constraints. Allocation may be performed first for any pending jobs which were partially released during a previous time interval, and then to new jobs in decreasing order of determined job rank. If different operative constraints dictate different numbers of units of a job to be released, the minimum number of units meeting each constraint may be released. After the number of units to be released has been determined for a job, machine information is updated to account for available capacity consumed by the release of the selected number of units of the job. Updated information may be used for job release scheduling of the next job.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: February 6, 2007
    Assignee: Agency for Science, Technology and Research
    Inventors: Tay Jin Chua, Tian Xiang Cai, Ming Wei William Liu, Feng Yu Wang
  • Patent number: 6744101
    Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: June 1, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei Long, Yowjuang William Liu, Don Wollesen
  • Publication number: 20040006490
    Abstract: An exchange hub having electronic connections to subscribers including prescribers, pharmacies and pharmacy benefit management services (PBMs) for the purpose of exchanging relevant pharmaceutical data is disclosed. The, exchange hub allows each of its subscribers to send communications that may include request and response transactions, an end point to end point message, or an upload of a data file. The communications may be opaque to the exchange hub or the contents may be modified for additional value. The communications may include a request for eligibility of benefits for a particular patients which will return an aggregation of all PBMs for which that patient is eligible. Additional patient information such as formularies or medication history may be requested. The exchange hub also may route prescription information between the prescriber and pharmacies.
    Type: Application
    Filed: December 30, 2002
    Publication date: January 8, 2004
    Inventors: Mark A. Gingrich, H. John Beardsley, Teresa M. Byrne, Scott Robert Deasy, Trevor S. Gruby, Alan K. Jackson, Bryan T. Koch, Paul Lemley, William Liu, Frank V. McKinney, Todd Richard Simenson, DeNyce Steadland, David Tauzell, Gary B. Udstrand, Mark Udstrand, Jeffrey R. Whiteside
  • Patent number: 6528847
    Abstract: A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (dc), and contoured edges. The depth (dc) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (dj) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Yowjuang William Liu
  • Patent number: 6407558
    Abstract: A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: June 18, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil N. Shabde, Yowjuang William Liu, Ting Yiu Tsui
  • Publication number: 20020000635
    Abstract: A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (dc), and contoured edges. The depth (dc) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (dj) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling.
    Type: Application
    Filed: June 29, 1998
    Publication date: January 3, 2002
    Inventor: YOWJUANG WILLIAM LIU
  • Patent number: 6320403
    Abstract: A method (100) of determining a doping type and a doping concentration of a semiconductor material (101) includes the steps of moving carriers (103) in the material, wherein a number of carriers is a function of the doping concentration of the material (101) and a type of carriers is a function of the doping type of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: November 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil N. Shabde, Yowjuang William Liu, Ting Yiu Tsui
  • Patent number: 6309949
    Abstract: A process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of obtaining a semiconductor substrate patterned with a plurality of mesas with sidewalls, each of the mesas comprising at least a first insulator layer and a second different insulated layer thereover, forming a trench between the mesas into the semiconductor substrate, removing a lateral portion of the first insulator layer exposed at the sidewalls of the mesas to thereby undercut the second insulator layer at its sidewall edges, forming an oxide layer on exposed areas of the semiconductor substrate below the undercut of the second insulator layer, and filling the trench with an insulator material.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: October 30, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yue Song He, Yowjuang William Liu
  • Patent number: 6294829
    Abstract: A quadruple gate field effect transistor (FET) is provided on the semiconductor-on-insulator or semiconductor-on-insulator (SOI) structure or a bulk semiconductor structure. The silicon substrate is surrounded by a polysilicon material on at least three sides to form a gate. Additionally, the substrate can be surrounded by a fourth side to form a quadruple gate structure. The SOI structure can be comprised of two layers of SOI structures. Interlayer vias can be provided to connect each layer of the two-layer structure.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: September 25, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Yowjuang William Liu
  • Publication number: 20010017390
    Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.
    Type: Application
    Filed: March 15, 2001
    Publication date: August 30, 2001
    Inventors: Wei Long, Yowjuang William Liu, Don Wollesen
  • Publication number: 20010011895
    Abstract: A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).
    Type: Application
    Filed: December 15, 2000
    Publication date: August 9, 2001
    Inventors: Sunil N. Shabde, Yowjuang William Liu, Ting Yiu Tsui
  • Patent number: 6248629
    Abstract: A method for manufacturing a non-volatile memory device, the device having a core memory cell region and a periphery region, comprising the steps of: forming memory cell gate structures in the core memory cell region; forming active regions adjacent to the gate structure through a blanket implant; forming an implant/etch mask; implanting an impurity into one of the active regions; etching an oxide layer in the implant region; and forming active devices in the periphery region. In a further aspect, the method comprises method of performing a self aligned source etch in forming a memory device, comprising: forming resist spacers adjacent to the channel regions of the memory device; and etching the oxide layer.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: June 19, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yow-Juang William Liu, Gu Fung David Tsuei, Jian Chen
  • Patent number: 6225669
    Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: May 1, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei Long, Yowjuang William Liu, Don Wollesen
  • Patent number: 6208154
    Abstract: A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: March 27, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil N. Shabde, Yowjuang William Liu, Ting Yiu Tsui
  • Patent number: 6177802
    Abstract: A system for detecting defects in an interlayer dielectric (ILD) interposed between first and second conductive lines lying adjacent each other along a first plane is provided. A processor controls general operations of the system. A voltage source adapted to apply a bias voltage between the first and second conductive lines is employed to induce a leakage current across the ILD. A light source for illuminating at least a portion of the ILD is used to enhance the leakage current. A magnetic field source applies a magnetic field in a direction orthogonal to the leakage current. The magnetic field deflects carriers in a direction substantially perpendicular to the first plane. A voltage monitor measures a voltage generated across third and fourth conductive lines, the third and fourth conductive lines lying adjacent each other along a second plane which is substantially perpendicular to the first plane. The voltage monitor is operatively coupled to the processor.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: January 23, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil N. Shabde, Yowjuang William Liu, Ting Yiu Tsui