Patents by Inventor William Loftin

William Loftin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
    Patent number: 7195984
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, William Loftin, William F. Kyser, Jr.
  • Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor
    Publication number: 20070045732
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).
    Type: Application
    Filed: August 3, 2005
    Publication date: March 1, 2007
    Applicant: Texas Instruments Inc.
    Inventors: John Lin, Tony Phan, Philip Hower, William Loftin, Martin Mollat
  • Integrated circuit having a top side wafer contact and a method of manufacture therefor
    Publication number: 20070029611
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
    Type: Application
    Filed: August 2, 2005
    Publication date: February 8, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Tony Phan, William Loftin, John Lin, Philip Hower
  • Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
    Publication number: 20050087812
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Application
    Filed: November 22, 2004
    Publication date: April 28, 2005
    Inventors: Joe Trogolo, William Loftin, William Kyser
  • Diode having a double implanted guard ring
    Publication number: 20050040489
    Abstract: The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the substrate and doped with a second type dopant opposite the first type dopant and having a first doped profile region 245a and a second doped profile region 245b. The present invention also includes a method of manufacturing this diode and an integrated circuit that utilizes this diode 200 within a CMOS and bipolar transistor integrated circuit 600.
    Type: Application
    Filed: August 20, 2003
    Publication date: February 24, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Ming-Yeh Chuang, William Loftin, Scott Montgomery
  • Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
    Patent number: 6856000
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: February 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, William Loftin, William F. Kyser, Jr.
  • Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
    Publication number: 20040065942
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Inventors: Joe R. Trogolo, William Loftin, William F. Kyser,