Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: A DDR non-volatile memory providing Double Data Rate (DDR) operation by decoding an address received from an external processor at a DDR interface to provide a command to store data in page buffers. The data received from the external processor at the DDR interface is transferred to page buffers based on the command. A command issued by an internal microcontroller transfers data stored in the page buffers to non-volatile storage.

Abstract: Natural gas liquefaction system employing an enhanced nitrogen removal system capable of removing nitrogen from a relatively warm natural gas stream.

Abstract: Multiple independent images are presented on multiple display devices by driving the display devices with a common set of control signals and a multiplexed set of data signals that convey information representing interleaved components of each independent image. In a preferred embodiment, a unique clock signal is provided to each respective display device that is aligned with the interleaved components of the image to be presented by that respective display. The control, data and clock signals may be obtained by multiplexing control and data signals received from display pipeline circuits, or by generating the, signals using a composite circuit that implements the features of two or more multiplexed display pipeline circuits.

Abstract: A clocking system including a line clock system for generating normal line clock pulses to the digital display during the period when the image is being rendered and for generating fast line clock pulses to the digital display during the vertical blanking period to address the otherwise unaddressed vertical region. The clocking system further includes a pixel clock system for generating normal pixel clock pulses to the digital display during the period when the image is being rendered and for generating fast pixel clock pulses to the digital display during the horizontal and vertical blanking periods to address the otherwise unaddressed horizontal and vertical regions.

Abstract: An electric fence controller for controlling the charge on an electrified fence. A charging circuit is provided which includes a ferro-resonant input transformer. The transformer is provided with primary and secondary windings wound on separate legs of a saturable core. A capacitor is connected across the secondary winding and forms a resonant circuit with the secondary winding. An energy storing capacitive circuit is connected to the charging circuit. A voltage multiplying output circuit is connected to the capacitive circuit through a switching circuit. This arrangement enables the input to the transformer to be electrically isolated from the output circuit.