Abstract: Techniques for selecting and loading a correct initialization software module for managing communication by a scanner with a terminal over a universal serial bus connection are described. A bootloader is transferred from semipermanent memory to RAM and executed. The bootloader detects a configuration in which a scanner is being used, selects a correct initialization for use with the scanner and copies an interrupt service request table for the selected module to an image of the bootloader in the semipermanent memory. The image of the bootloader is then transferred to RAM, with the interrupt service request table being stored in an appropriate location in RAM. The bootloader then transfers an executable code block for the selected initialization module from the semipermanent memory to the RAM for execution.

Abstract: Disclosed is a Software Sanity Monitor for automatically detecting and remedying software lock-up conditions without user intervention. Users often refer to these conditions as “hangs” or “forever loops”. Although the Software Sanity Monitor uses the operating software's information, it is designed to execute independent of the operating system software; thereby, eliminating reliance on a “sane” operating system. If a “hang” condition is detected, the Software Sanity Monitor will automatically restart the system after logging the failure and, optionally, notify the user or host system.

Abstract: An optical scanner for reading two-dimensional bar code labels. A rotating reflector directs a laser beam towards a plurality of pattern mirrors during a first mode of operation to produce a plurality of different scan lines forming a multi-line scan pattern for collecting light from an article having a one-dimensional bar code label, and directs the laser beam towards one of the pattern mirrors during a second mode of operation to produce a single scan line for collecting light from an article having a two-dimensional bar code label. A single tilted mirror assembly, having a motor for rotating a drive shaft and a mirror mounted at an angle to the drive shaft, reflects the plurality of different scan lines towards the article having the one-dimensional bar code label during the first mode of operation, and reflects the one scan line from the scan module towards the article having the two-dimensional bar code label during the second mode of operation.

Abstract: A price verifier which is smaller in size than existing price verifiers and which includes additional features which provide enhanced functionality and ease of use. The price verifier includes a bar code reader for reading a bar code label on an item whose price is to be verified. Control circuitry obtains the price of the scanned item from a host terminal. A display displays the price of the item. The price verifier supports multiple communications protocols, including wireless RF. Additionally, the price verifier may be programmed by reading programming bar code labels or by downloading program commands from the host terminal.

Abstract: An automatic sensing and programming circuit for optical scanners which produces a diffuse volume of light substantially encompassing the scan volume of the scanner. A method for programming one optical scanner from another uses the circuit to emit a plurality of pulse trains which in combination represent a predetermined function or set of functions, each pulse train representing predetermined hexadecimal digit, and each pulse train including a predetermined number of binary pulses. A method of programming an optical scanner employs a plurality of tags which in combination represent a predetermined function or set of functions, each tag representing a predetermined hexadecimal digit encoded as bar code labels.

Abstract: A system for controlling the transfer of a data message over a common communication channel between a plurality of processing devices includes a MOS/LSI controller chip associated with each processing unit for constructing a message to be sent to a sending device acknowledging the receipt of the message and the validity of the message. Logic circuits are included which generate a predetermined sequence of two binary bits indicating the receipt of the message and the validity of the receiving message. The binary bits are framed by two other binary bits and the sequence repeated a predetermined number of times to construct an acknowledgment message. The controller chip further includes logic circuits for decoding the acknowledgment message.

Abstract: A system is disclosed for selectively serially coupling a plurality of stations in a communications network into a single communications path. In the system of the invention, a plurality of tap boxes are serially coupled into the single communications path. Each station is coupled to a desired associated one of the tap boxes by way of an associated tap cable. When the tap cable is connected to a first portion of the tap box, a first impedance corresponding to the characteristic impedance of the single communications path is serially coupled into the single communications path to enable the station associated with the tap cable to be coupled to the single communications path by way of the first impedance. When the tap cable is connected to a second portion of the tap box, the first impedance is effectively removed from the single communications path and a test impedance is coupled to the tap cable to enable the station associated with the tap cable to test itself.

Abstract: A system for controlling the flow of data over a common bus between a plurality of processing units is disclosed which preferably includes a MOS/LSI circuit controller chip associated with each processing unit for awarding priority of access to the common bus when two or more processing units attempt to simultaneously gain access to the common bus. A contention circuit located in each controller chip is responsive to the sensing of each bit in the address of its associated processing unit, and generates a plurality of transitions on the common bus during the time a binary one bit is sensed in the address and listens for the presence of any transition on the common bus during the time a binary zero is sensed in the address. Access to the common bus is lost when transitions are detected on the bus during the time a binary zero bit is sensed and acquired when no transitions have been detected at the completion of the sensing of the address of the requesting processing unit.