Abstract: A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.

Abstract: A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.

Abstract: A computer implemented method, apparatus, and computer program product for optimizing a non-uniform memory access system. Each thread in a set of threads is affinitized to a processor in a set of processors at different times to form a temporarily affinitized thread, wherein a single temporarily affinitized thread is present. The set of threads execute on the set of processors to perform one or more tasks each time the temporarily affinitized thread is formed. Information is collected about memory accesses by the temporarily affinitized thread. Based on the collected information about the memory accesses, at least one thread in the set of threads is permanently affinitized to a processor in the set of processors.

Abstract: A method, system, and computer program product enable the selective adjustment in the size of memory pages allocated from system memory. In one embodiment, the method includes, but is not limited to, the steps of: collecting profile data (e.g., the number of Translation Lookaside Buffer (TLB) misses, the number of page faults, and the time spent by the Memory Management Unit (MMU) performing page table walks); identifying the top N active processes, where N is an integer that may be user-defined; evaluating the profile data of the top N active processes within a given time period; and in response to a determination that the profile data indicates that a threshold has been exceeded, promoting the pages used by the top N active processes to a larger page size and updating the Page Table Entries (PTEs) accordingly.