Abstract: A digital data transceiver comprises a conventional push-pull driver and a novel receiver. The transceiver can drive data to and simultaneously receive data from a transceiver of like kind via the same communication line. A series resistor is situated between the driver's output and the communication line. The resistor has equivalent resistance to the characteristic impedance of the line in order to prevent undesirable reflections on the line. In the receiver, the driver's output is divided in half by a resistor voltage divider for input to a differential current mechanism. The differential current mechanism has a differential current switch and a feedback circuit. The differential current switch compares the signal levels at both ends of the series resistor to derive an output for the receiver. The feedback circuit provides feedback to the differential current switch to increase the noise margin.

Abstract: A low power push pull off chip driver for differential cascode current circuitry is described that includes the collectors of a differential pair directly coupled to bases of a push pull driver and level shifters coupled to the input of the differential pair to prevent saturation of the differential pair.

Abstract: A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.

Abstract: An FET load gate compensator employing feedback to control the load gate voltage holds the circuit delay and power dissipation of an integrated circuit nearly constant. The integrated circuit chip is provided with several stages of inverters which act as a delay sensor to simulate the delay of the operational circuit on the chip. The time delay of the delay sensor on the integrated circuit chip is compared with an external clock reference by a delay comparator. The delay comparator generates an output voltage which is used to adjust the load gate voltage until the delay in the delay sensor is equal to the clock reference. Since the same load gate voltage is distributed in the rest of the operational circuits in the integrated circuit chip, the delay times of these circuits will track with that of the delay sensor and thus also tend to be held constant.

Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.