Patents by Inventor William M. Coppock

William M. Coppock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7507607
    Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock, Jeffery L. Nilles, Andy Strachan
  • Patent number: 7172973
    Abstract: A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: February 6, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Richard W. Foote, William M. Coppock, Victor M. Torres, Terry Lines
  • Patent number: 7118998
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock
  • Patent number: 6930010
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: William M. Coppock, Charles A. Dark
  • Patent number: 6815797
    Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: November 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock, Jeffery L. Nilles, Andy Strachan
  • Patent number: 6815714
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: November 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: William M. Coppock, Charles A. Dark
  • Patent number: 6812486
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: November 2, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock
  • Patent number: 6563189
    Abstract: The present invention provides a two-terminal Zener zap diode device structure that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flow of an aluminum alloy to create the current path. The use of oversized contacts in the diode structure permits the Tungsten plug to be eliminated from the diode structure and, thus, permits an aluminum alloy melt and flow mechanism to be used with a Tungsten plug process.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: May 13, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Charles Dark, William M. Coppock
  • Patent number: 6440781
    Abstract: A three-terminal integrated circuit device structure is provided that relies upon the formation of an anti-fuse through a silicon substrate with the melting and flowing of an aluminum/aluminum alloy to create the current path. The use of an oversized contact permits the Tungsten plug to be eliminated from the anti-fuse structure, but allows the aluminum melt and flow mechanism to be used with a Tungsten plug process.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: August 27, 2002
    Assignee: National Semiconductor Corporation
    Inventors: William M. Coppock, Charles Dark
  • Patent number: 5686857
    Abstract: A triac (100) utilizes an FET (107) to inhibit firing of a transistor (112) that forms a portion of the SCR of the triac (100). A DMOS transistor (106) is used to supply a substantially constant bias current to the transistor (107) in order to facilitate rapid turn-on of the transistor (107) around the zero-crossing of the voltage applied to the triac (100).
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: November 11, 1997
    Assignee: Motorola, Inc.
    Inventors: David M. Heminger, Paul G. Alonas, William M. Coppock