Abstract: Managing camera outputs in an interactive multi-display surrounding view system comprises: receiving outputs from at least four cameras of the vehicle; stitching together the outputs into a first image of a top-down view of vehicle surroundings; adding a three-dimensional (3D) model of the vehicle to the first image, based on the vehicle surroundings, to generate a first enhanced image; and simultaneously presenting (i) the first enhanced image on a first display device of the vehicle, the first display device providing a first touchscreen input control for a first aspect of the first enhanced image, and (ii) a second image on a second display device of the vehicle, the second image comprising one of the outputs, the second display device providing a second touchscreen input control for a second aspect of the second image, wherein the first and second touchscreen input controls accept inputs simultaneously and non-simultaneously with each other.

Abstract: Managing camera outputs in an interactive multi-display surrounding view system comprises: receiving outputs from at least four cameras of the vehicle; stitching together the outputs into a first image of a top-down view of vehicle surroundings; adding a three-dimensional (3D) model of the vehicle to the first image, based on the vehicle surroundings, to generate a first enhanced image; and simultaneously presenting (i) the first enhanced image on a first display device of the vehicle, the first display device providing a first touchscreen input control for a first aspect of the first enhanced image, and (ii) a second image on a second display device of the vehicle, the second image comprising one of the outputs, the second display device providing a second touchscreen input control for a second aspect of the second image, wherein the first and second touchscreen input controls accept inputs simultaneously and non-simultaneously with each other.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: Methods and systems are disclosed for increased speed of processing operations on data in two-dimensional arrays, and for detecting a feature in an image. A method for detecting a feature in an image comprises storing, in a set of data memories within a parallel processing system, first image data representing pixels of a first image. The method further comprises storing, in a memory of a host processor coupled to the parallel processing system, feature kernel data representing a set of weight matrices. A method for increased speed of processing operations on data in two-dimensional arrays comprises storing, in a set of data memories within a parallel processing system, first array data representing elements of a first array. The method further comprises, for each of multiple selected elements within the first array, performing a processing operation on the selected element to produce an output element corresponding to the selected element.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host-program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.

Abstract: Methods and systems are disclosed for increased speed of processing operations on data in two-dimensional arrays, and for detecting a feature in an image. A method for detecting a feature in an image comprises storing, in a set of data memories within a parallel processing system, first image data representing pixels of a first image. The method further comprises storing, in a memory of a host processor coupled to the parallel processing system, feature kernel data representing a set of weight matrices. A method for increased speed of processing operations on data in two-dimensional arrays comprises storing, in a set of data memories within a parallel processing system, first array data representing elements of a first array. The method further comprises, for each of multiple selected elements within the first array, performing a processing operation on the selected element to produce an output element corresponding to the selected element.

Abstract: Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

Abstract: Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host-program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: A communication system for providing world-wide, mobile Internet communication to a plurality of users and a method therefore. The system includes ground-based, multi-channel, radio frequency transmitting and receiving broadcasting grids that are capable of providing content to multiple users via cell towers and low-altitude, optical transmitting and receiving satellites that are in optical communication with the ground-based, multi-channel, RF transmitting and receiving broadcasting grids. The method includes transmitting optical and/or RF signals between at least one of the ground-based, multi-channel, RF transmitting and receiving broadcasting grids and at least one of the low-altitude, optical transmitting and receiving satellites.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: A communication system for providing world-wide, mobile Internet communication to a plurality of users and a method therefore. The system includes ground-based, multi-channel, radio frequency transmitting and receiving broadcasting grids that are capable of providing content to multiple users via cell towers and low-altitude, optical transmitting and receiving satellites that are in optical communication with the ground-based, multi-channel, RF transmitting and receiving broadcasting grids. The method includes transmitting optical and/or RF signals between at least one of the ground-based, multi-channel, RF transmitting and receiving broadcasting grids and at least one of the low-altitude, optical transmitting and receiving satellites.

Abstract: A method of controlling inertial attitude of an artificial satellite in order to perform a navigation function and to maximize terrestrial coverage of the Earth by the satellite. The method includes deploying the artificial satellite in an orbit about the poles of the Earth; applying gyroscopic precession to the artificial satellite spin axis to precess and maintain the satellite near the ecliptic pole; deploying the artificial satellite so that the spin axis is initially perpendicular to or substantially perpendicular to sun lines; and applying gyroscopic precession to the artificial satellite spin axis to precess the spin axis away from an initial deployed attitude at a selectively-variable precession rate and to maintain the spin axis perpendicular to or substantially perpendicular to the sun lines.

Abstract: A method of and apparatus for determining and controlling the inertial attitude of a spinning artificial satellite without using a suite of inertial gyroscopes. The method and apparatus operate by tracking three astronomical objects near the Earth's ecliptic pole and the satellite's and/or star tracker's spin axis and processing the track information.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: A communication system for providing world-wide, mobile Internet communication to a plurality of users and a method therefore. The system includes ground-based, multi-channel, radio frequency transmitting and receiving broadcasting grids that are capable of providing content to multiple users via cell towers and low-altitude, optical transmitting and receiving satellites that are in optical communication with the ground-based, multi-channel, RF transmitting and receiving broadcasting grids. The method includes transmitting optical and/or RF signals between at least one of the ground-based, multi-channel, RF transmitting and receiving broadcasting grids and at least one of the low-altitude, optical transmitting and receiving satellites.