Abstract: A computer memory system for use with a user processor provides automatic memory operations independently of the user processor. The memory system includes a logical memory system which is accessed by the user processor through a binding register unit, enabling the user processor to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The user cannot access the memory directly, but must access the memory through the binding registers. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the user processor.

Abstract: A visible light and near infrared imaging device is disclosed. The imaging device comprises X-Y addressing means, an array of opto-electronic semiconductor elements or cells, a multiplexer, a precharge switch, and an amplifier. The X-Y addressing means selectively addresses each cell of the array of opto-electronic semiconductor cells and corresponding multiplexer switch for connecting a reference voltage to each cell to charge each element to the reference voltage, then to isolate each element and vary its voltage in proportion to the intensity of the impinging light, and finally to read out selectively the voltage of each element to the amplifier for amplifying the electrical signals representative of the light intensity to a working level for processing into video signals.

Abstract: A delta frame circuit is disclosed. The delta frame circuit is connected to the video output of, for example, an imaging system for the purpose of producing a moving target indication radar or, for example, a chopped imaging system for the purpose of removing fixed pattern or undesirable offset voltages. The delta frame circuit comprises a plurality of capacitors having top plates connected to the video output and lower plates connected to the drains of a first plurality of field effect transistors. The gates and sources of these field effect transistors are connected, respectively, to a Y address circuit and drains of a second plurality of field effect transistors. The gates and sources of these field effect transistors are connected, respectively, to a X address circuit and to the drains of a third plurality of field effect transistors whose gates and sources are connected, respectively, to the Y address circuit, and junction of a precharge reference voltage and output amplifier.

Abstract: An improved ferroelectric imaging system comprises a chopper, lens system, ferroelectric detector matrix, switching matrix, drive and readout electronics, video processor and display. The chopper interrupts infrared energy emanating from a scene, and the lens system focuses the chopped infrared energy on the ferroelectric detector matrix which produces electrical signals representative of the impinging infrared energy. The signals are read out by the drive and read out electronics whose action is synchronized with the chopper action, processed in the video processor and displayed by the display. The ferroelectric matrix comprises a plurality of detector capacitor elements fabricated by forming a metal surface on the upper surface of a dielectric of ferroelectric material and a plurality of metal pads arranged in rows and columns on its lower surface. Said metal plate forming the upper plates for the capacitors and the metal pads forming the lower plates. The upper plate is connected to busbars for biasing.