Patents by Inventor William M. Siu

William M. Siu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
    Patent number: 7030479
    Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventors: William M. Siu, Bidyut K. Bhattacharyya
  • Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
    Publication number: 20040061223
    Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 1, 2004
    Inventors: William M. Siu, Bidyut K. Bhattacharyya
  • Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
    Patent number: 6664620
    Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: December 16, 2003
    Assignee: Intel Corporation
    Inventors: William M. Siu, Bidyut K. Bhattacharyya
  • INTEGRATED CIRCUIT DIE AND/OR PACKAGE HAVING A VARIABLE PITCH CONTACT ARRAY FOR MAXIMIZATION OF NUMBER OF SIGNAL LINES PER ROUTING LAYER
    Publication number: 20010045633
    Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.
    Type: Application
    Filed: June 29, 1999
    Publication date: November 29, 2001
    Inventors: WILLIAM M. SIU, BIDYUT K. BHATTACHARYYA
  • Standardized power and ground design for pin grid array packages
    Patent number: 5483099
    Abstract: An integrated circuit package that is coupled to a printed circuit board by a socket assembly. The socket assembly has a plurality of pins that are mounted to the circuit board. The pins are coupled to corresponding conductive sockets and outer rings of the socket assembly. The package contains an integrated circuit that is coupled to external pins which extend from a bottom surface of the package housing. The package also has a plurality of conductive rings that are located on the bottom surface of the housing and are electrically coupled to the integrated circuit. To install the package, the package pins are inserted into the individual sockets of the socket assembly. Insertion of the pins also presses the conductive rings of the package onto the corresponding outer rings of the socket. The conductive rings are typically dedicated to the power and ground pins of the system, wherein the integrated circuit receives power through the rings.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: January 9, 1996
    Assignee: Intel Corporation
    Inventors: Siva Natarajan, Udy Shrivastava, William M. Siu, Mark J. Palmer