Abstract: An apparatus for converting a digital input signal to an analog signal for transmission. The input signal can include more than one carrier signal. A plurality of delta-sigma modulation loop circuits are connected in an increasing order of operating frequency so as to reduce a word length of the input signal. A tuning circuit adjusts the signal frequency to a transmitting frequency for conversion to analog by a digital-to-analog converter. A first loop circuit is implemented using CMOS gates, and a second loop circuit and the tuning circuit are implemented using indium phosphide gates. The apparatus allows a high-resolution, wide-band RF multiple-carrier signal to be re-quantized to a lower-resolution signal while an acceptable signal-to-noise ratio is maintained.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC (20) employs delta-sigma processing to provide digital conversion over the complete frequency band.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.

Abstract: A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.

Abstract: A channelizer (22) for a multi-carrier receiver including a plurality of digital sub-band tuners (DSBTs) (274). Each DSBT (274) digitally filters individual carrier data bits from a digital multi-carrier data stream based on a programmable center frequency. Each DSBT (274) further digitally filters the individual carrier data stream based on a programmable bandwidth. The DSBTs (274) can be allocated based on modulation format, center frequency, or both. The channelizer (22) is therefore able to process narrowband carrier data streams as well as wideband carrier data streams. One embodiment of the channelizer (22) has a plurality of sub-channelizers (22) and a switch matrix (278). The sub-channelizers (22) filter individual carrier data streams from a multi-carrier data stream. The switch matrix (278) is coupled to the sub-channelizers (22) and routes the individual data streams to the sub-channelizers (22) in a desired configuration.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: An apparatus for converting a digital input signal to an analog signal for transmission. The input signal can include more than one carrier signal. A plurality of delta-sigma modulation loop circuits are connected in an increasing order of operating frequency so as to reduce a word length of the input signal. A tuning circuit adjusts the signal frequency to a transmitting frequency for conversion to analog by a digital-to-analog converter. A first loop circuit is implemented using CMOS gates, and a second loop circuit and the tuning circuit are implemented using indium phosphide gates. The apparatus allows a high-resolution, wide-band RF multiple-carrier signal to be re-quantized to a lower-resolution signal while an acceptable signal-to-noise ratio is maintained.

Abstract: An analog-to-digital converter (170) that employs delta-sigma technology, and has particular use in a receiver for a wireless telecommunications system. The converter (170) includes a delta-sigma modulator (172), having a summing junction (180) that receives the analog input signal to be converted. A feedback from the output of a comparator (186) is subtracted from the analog input signal to generate a difference signal that is then filtered, amplified and applied to the comparator (186) for digital conversion. A sample and hold circuit (184) receives the difference signal and holds the signal for a predetermined period of time so that the input to the comparator (186) is stable. A differential limiting amplifier (188) is employed to make the high data rate output of the comparator (186) stable. The differential limiting amplifier (188) can be within the comparator (186) itself, or in the feedback path. In one embodiment, the differential amplifier (188) employs a Schottky diode clamp (226).