Abstract: A hardware implementation of a rank order filter includes inputs for inputting a window parameter or window size signal and a target rank signal, thereby permitting programming of the rank order filter to perform rank order filtering within any specified window and relative to any desired target rank.

Abstract: Signal processing techniques are disclosed for applications such as finite impulse response filtering. After initial processing in residue number system (RNS) channels, the signals are converted from residue form to a true external representation of the filter output. The conversion employs a chinese remainder theorem decoder and shift accumulator controlled to utilize adaptive modulo reduction. As a consequence, each modulus function value is reduced during computation when it exceeds the modulus and not at the end of the function evaluation. This reduces hardware requirements by minimizing the arithmetic word length. In implementing the technique, each function value is tested to see if it is within a modulus range and the corresponding modulus value is subtracted if it is not. This is done as many times as is necessary to bring each function value within the range.

Abstract: A digital circuit is disclosed for computing the magnitude of a complex number employing piece-wise linear approximations to achieve precision without the need for iteration. An illustrative implementing circuit employs a first stage for converting the in-phase and quadrature signals to their absolute values. The resultant signals are applied to a selection circuit which selects the maximum and minimum values. The resultant signals are combined with coefficients selected as a function of the operating interval and the resultant products added to yield a signal related to the magnitude of the input complex number.