Patents by Inventor William Mark Hiatt
William Mark Hiatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446440Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: August 21, 2018Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20180358263Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 10062608Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: May 2, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20170283954Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: May 2, 2017Publication date: October 5, 2017Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 9640433Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: GrantFiled: February 10, 2014Date of Patent: May 2, 2017Assignee: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Publication number: 20140154879Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.Type: ApplicationFiled: February 10, 2014Publication date: June 5, 2014Applicant: Micron Technology, Inc.Inventors: Salman Akram, James M. Wark, William Mark Hiatt
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Patent number: 8324100Abstract: Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.Type: GrantFiled: February 17, 2011Date of Patent: December 4, 2012Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steven Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 8294273Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: GrantFiled: January 6, 2011Date of Patent: October 23, 2012Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Publication number: 20120154945Abstract: In one aspect, the present invention provides wafer level optical assemblies comprising one or more optical apertures spaced apart from optical wafers and/or optical wafer substrates. In some embodiments, a wafer level assembly described herein comprises a first wafer comprising a first perforation and a first aperture aligned with the first perforation and coupled to the first wafer.Type: ApplicationFiled: December 16, 2010Publication date: June 21, 2012Inventor: William Mark Hiatt
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Publication number: 20110136336Abstract: Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.Type: ApplicationFiled: February 17, 2011Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Salman Akram, William Mark Hiatt, Steven Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Publication number: 20110095429Abstract: Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: ApplicationFiled: January 6, 2011Publication date: April 28, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 7892972Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.Type: GrantFiled: February 3, 2006Date of Patent: February 22, 2011Assignee: Micron Technology, Inc.Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
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Patent number: 7709776Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.Type: GrantFiled: February 20, 2009Date of Patent: May 4, 2010Assignee: Aptina Imaging CorporationInventors: Warren M. Farnworth, Sidney B. Rigg, William Mark Hiatt, Alan G. Wood, Peter A. Benson, James M. Wark, David R. Hembree, Kyle K. Kirby, Charles M. Watkins, Salman Akram
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Patent number: 7632713Abstract: Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, the microelectronic imaging devices include an interposer substrate and a plurality of imager units coupled to the interposer substrate. The interposer substrate includes a plurality of openings and a plurality of contact arrays proximate to corresponding openings. The individual imager units include a microelectronic die with an image sensor and a plurality of bond-pads electrically coupled to the image sensor. The image sensors are aligned with corresponding openings on the interposer substrate, and the bond-pads are electrically coupled to corresponding contacts on the interposer substrate.Type: GrantFiled: April 27, 2004Date of Patent: December 15, 2009Assignee: Aptina Imaging CorporationInventors: Warren M. Farnworth, William Mark Hiatt
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Publication number: 20090155949Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.Type: ApplicationFiled: February 20, 2009Publication date: June 18, 2009Inventors: Warren M. Farnworth, Sidney B. Rigg, William Mark Hiatt, Alan G. Wood, Peter A. Benson, James M. Wark, David R. Hembree, Kyle K. Kirby, Charles M. Watkins, Salman Akram
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Patent number: 7504615Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.Type: GrantFiled: March 27, 2007Date of Patent: March 17, 2009Assignee: Aptina Imaging CorporationInventors: Warren M. Farnworth, Sidney B. Rigg, William Mark Hiatt, Alan G. Wood, Peter A. Benson, James M. Wark, David R. Hembree, Kyle K. Kirby, Charles M. Watkins, Salman Akram
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Patent number: 7470563Abstract: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.Type: GrantFiled: October 11, 2005Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventors: William Mark Hiatt, Warren Farnworth
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Patent number: 7452743Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.Type: GrantFiled: September 1, 2005Date of Patent: November 18, 2008Assignee: Aptina Imaging CorporationInventors: Steven D. Oliver, Lu Velicky, William Mark Hiatt, David R. Hembree, Mark E. Tuttle, Sidney B. Rigg, James M. Wark, Warren M. Farnworth, Kyle K. Kirby
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Patent number: 7265330Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.Type: GrantFiled: June 28, 2006Date of Patent: September 4, 2007Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Sidney B. Rigg, William Mark Hiatt, Alan G. Wood, Peter A. Benson, James M. Wark, David R. Hembree, Kyle K. Kirby, Charles M. Watkins, Salman Akram
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Patent number: 7189954Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.Type: GrantFiled: July 19, 2004Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Sidney B. Rigg, William Mark Hiatt, Alan G. Wood, Peter A. Benson, James M. Wark, David R. Hembree, Kyle K. Kirby, Charles M. Watkins, Salman Akram