Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a lead frame including a major surface, and a die having including a bond pad. A wire may electrically couple a location of the major surface of the lead frame with the bond pad of the die, the wire being situated such that the wire is substantially unbent from the location of the major surface to an edge of the lead frame.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.

Abstract: Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.