Abstract: A humidification system can include a heater base, a humidification chamber, and a breathing circuit. A cartridge can be removably coupled to the heater base. The cartridge can include various sensors, probes, sensor wire connectors, heater wire connectors, and/or other features. The cartridge can include features configured to mate with corresponding features on the humidification chamber and the heater base. The cartridge includes a memory, such as an EEPROM, or other suitable storage device. When the cartridge is installed on the heater base, the memory is electrically connected to a processor and/or memory of the heater base. Various models of cartridges can be produced for use with different humidification chambers, breathing circuits, and/or therapies. A connector can be configured to couple an inspiratory conduit to an outlet port of the humidification chamber. The connector can provide a pneumatic connection to the outlet port and an electrical connection to the cartridge.

Abstract: The present invention relates to compounds of formula I: and pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising the compounds of formula I or their pharmaceutically acceptable salts, and methods of using said compounds, salts and compositions in the treatment of various disorders associated with CRM1 activity.

Abstract: A circuit connector for a humidification system, the system comprising a base unit configured to be engaged by a humidification chamber. The circuit connector comprises an inlet to fluidly connect to an outlet of the humidification chamber to receive humidified gases therefrom, an outlet to sealably connect to or integral with a conduit for directing the humidified gases to a user, and an electrical terminal for electrically coupling the circuit connector to an electrical terminal associated with the base unit. The circuit connector may be releasably and lockably connectable to the outlet of the humidification chamber and/or orientation features may control orientation of component parts of the system as they are assembled.

Abstract: Computer program products, methods, systems, apparatus, and computing entities are provided for optimizing package delivery and confirmation are disclosed. In one embodiment, the system's processors accesses a first image of an assigned delivery location captured by a first computing device. The first image comprises an annotation indicating a specific location at the assigned delivery location for delivery of a parcel. At a display device of a second computing device, a real-time image stream comprising the annotation is captured by a camera of the second computing device is displayed. The annotation is overlaid within the real-time image stream based on comparing the first image received from the first computing device to the real-time image stream. The system further captures, from the real-time image stream, a second image when the parcel is positioned at the specific location based on the annotation overlaid within the real-time image stream.

Abstract: An engine combustion air pre-cleaner includes a body shaped for effecting cyclonic air flow between an inlet and an outlet of the body. Located along a longitudinal axis of the body is a conical throttling member which is coupled to a control device which operates in response to increasing engine load, as represented by increasing boost pressure, torque and/or speed, to shift the throttling member so as to cause an increasing air flow with increasing engine load.

Abstract: An engine combustion air pre-cleaner includes a body shaped for effecting cyclonic air flow between an inlet and an outlet of the body. Located along a longitudinal axis of the body is a conical throttling member which is coupled to a control device which operates in response to increasing engine load, as represented by increasing boost pressure, torque and/or speed, to shift the throttling member so as to cause an increasing air flow with increasing engine load.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: A probe for measuring particulates in molten metal includes an inner metal receiving chamber, with an orifice to permit metal to flow into the chamber. A first electrode extends into the chamber and a second electrode surrounds at least a portion of the chamber. The electrodes are connected to a measurement device for measuring changes in the electrical potential produced by the passage of particulates entrained in the molten metal passing through the orifice. An outer sheath of heat resistant material surrounds the second electrode and a gas passageway extends out of the inner tube for creating a pressure differential within the chamber for facilitating the flow of molten metal through the orifice. A liquidus depressing material is in the chamber to lower the liquidus temperature of the molten metal and permit a longer time period for detecting and measuring particulates in the molten metal.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: A probe for insertion into molten metal to detect and measure particulates suspended therein includes an inner tube of an electrically insulated material forming a metal receiving chamber, the tube having an orifice to permit molten metal to flow into the chamber. A first electrode extends into the chamber for engaging metal within the chamber and a second electrode surrounds at least a portion of the inner tube for engaging molten metal outside of the chamber. The electrodes may be connected to a measurement device for establishing a current path through the electrodes and passing through the orifice for measuring changes in the electrical potential produced by the passage of particulates entrained in the molten metal passing through the orifice.

Abstract: A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.

Abstract: An object-oriented processor and method of operating such a processor are disclosed. According to the method, in response to receiving a first instruction that references a first object having both data and at least a first method associated therewith, an address of the first method is calculated. In addition, at least one pointer is cached that indicates (possibly together with other pointers) the address of the first method. In response to receipt of a subsequent second instruction that references a second object having both data and one or more methods associated therewith, where the one or more methods include the first method, the address of a second method associated with the second object is determined by reference to the cached pointer. In a preferred embodiment of the present invention, the first and second methods comprise the same method, and the cached pointer indicates the entry point of that single method.

Abstract: A method and apparatus for assisting garbage collection process within a Java virtual machine are disclosed. A virtual object heap and a physical object heap are provided within the Java virtual machine, with the virtual object heap considerably larger than the physical object heap. Objects from Java applications are allocated within the virtual object heap. Each address of the allocated objects within the virtual object heap is translated into an address of a location within the physical object heap. Garbage collection is performed in the virtual object heap only when a total number of objects within the virtual object heap has reached a predetermined threshold.

Abstract: A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.