Abstract: A method for electrically connecting planar element substrates (12) to form an array (10) by forming conductive bridges (16) between metal pads (14) located on the surface of array elements (12). These bridges (16) are designed to transmit or receive visual, acoustical or other electromagnetic data and power. The conductive bridges (16) are formed to be nearly coplanar with the planar elements (12) and are made to connect the edges (14b) of pads (14) which are fused to the planar substrate (12). Metal wire (16a), solder (16b-c), a conductive polymer (16d), or a suspension of conductive particles in paste (16e) are used to bridge and electrically connect the pads (14) located on the array elements (12). The bridges (16) have a low profile, occupy a very small area and reduce the need for highly accurate alignment of adjacent substrates (12) within the tiled array (10) before electrical connections are formed.

Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.