Patents by Inventor William Michael Moller

William Michael Moller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6287970
    Abstract: A method of making a semiconductor device includes the steps of forming an oxide layer adjacent a semiconductor substrate, etching trenches within the oxide layer, depositing a copper layer to at least fill the etched trenches, and forming a copper arsenate layer on the deposited copper layer. The copper arsenate layer is then chemically mechanically polished. The copper layer may be deposited by at least one of electrodeposition, electroplating and chemical vapor deposition. The copper arsenate layer on the surface of the deposited copper layer inhibits oxidation and corrosion and stabilizes the microstructure of the deposited copper layer to thereby eliminate a need to subsequently anneal the deposited copper layer.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: September 11, 2001
    Assignee: Agere Systems Inc.
    Inventors: Sailesh Mansinh Merchant, Sudhanshu Misra, William Michael Moller, Pradip Kumar Roy
  • Patent number: 4107835
    Abstract: An improved Schottky barrier connection is made to a desired region of a silicon wafer by implanting the region with ions to peak at a particular depth; depositing a suitable contact material, such as platinum, over such region; and then heating the wafer to react the platinum and the silicon such that the interface between the platinum-silicide and the silicon penetrates beyond the peak depth of the implant, some of the encountered dopant ions being accumulated at the advancing interface in snowplow fashion. There results a narrowed and concentrated layer of implanted ions localized just below the interface of the silicide and the silicon. The presence of this layer permits conduction in the forward direction at lower applied voltages without substantially degrading the reverse blocking characteristics.
    Type: Grant
    Filed: February 11, 1977
    Date of Patent: August 22, 1978
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Jeffrey Bruce Bindell, Edward Franklin Labuda, William Michael Moller