Abstract: An integrated circuit (IC) package is described. The IC package includes a package die and die interconnects on an active surface of the package die. The IC package also includes an integrated passive device (IPD) coupled to the active surface of the package die, between the plurality of die interconnects. A portion of the IPD extends beyond a Z-height of the die interconnects. The IC package further includes a package substrate coupled to the die interconnects, the package substrate having a cavity to receive the portion of the IPD.

Abstract: An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

Abstract: An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

Abstract: An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.

Abstract: An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.

Abstract: Disclosed is a die packaging structure comprising a semiconductor die, an encapsulant layer disposed around the semiconductor die, wherein a backside surface of the semiconductor die is exposed, and a conductive layer coupled to the semiconductor die, the conductive layer comprising a plurality of conductive pillar bumps, wherein a bump density of the plurality of conductive pillar bumps is greater than 5%, wherein the encapsulant layer is further disposed between the plurality of conductive bumps, and wherein the encapsulant layer is disposed between the plurality of conductive bumps using a mold underfill (MUF) process. A method of forming the same is also disclosed.