Abstract: Apparatus and method for regulating data in a signal processing pipeline are disclosed. For example, an apparatus is disclosed that includes a first element operable to determine a time interval between a first plurality of data samples input to the signal processing pipeline, and calculate a sample spacing count value associated with the time interval, a second element coupled to the first element, the second element operable to hold the sample spacing count value until the time interval between the first plurality of data samples is changed, a third element coupled to the second element and the signal processing pipeline, the third element operable to output a control signal to the signal processing pipeline, and responsive to the control signal, the signal processing pipeline operable to output a second plurality of data samples.

Abstract: A Coordinate Rotation Digital Computer (CORDIC) circuit capable of performing precise vector rotation, including a pre-rotation stage configured to selectively rotate an input vector by ±90 degrees and to produce a pre-rotated vector. A first stage is configured to perform a first set of iterative CORDIC calculations on the pre-rotated vector and to produce a first rotated vector and a remaining rotation value. A second stage configured to perform a second set of iterative CORDIC calculations on the first rotated vector and to produce a second rotated vector, the second rotated vector corresponding to the input vector.

Abstract: The present disclosure relates generally to systems and methods for tuning power consumption and group delay in circuits such as radio frequency integrated circuits (RFICs). In one example, a system includes first and second gating blocks configured to reduce a first clock signal operating at a first clock rate to a second clock rate and a third clock rate, respectively. A first processing block coupled to the first gating block operates at the second clock rate. A second processing block is coupled to the first processing block and the second gating block, and operates at the third clock rate. The first processing block changes a flag state from a first state to a second state when transmitting a first data sample to the second processing block, and changes the flag state from the second state to the first state when transmitting a second data sample to the second processing block.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: An apparatus and method for flexible visibility in an integrated circuit are disclosed. As one example, an apparatus for flexible visibility in an integrated circuit is disclosed. The apparatus includes a switch unit disposed in the integrated circuit, the switch unit configured to receive a plurality of signals associated with a plurality of visibility points in the integrated circuit, and output the received plurality of signals in a serial form. Also, the apparatus includes a formatter unit disposed in the integrated circuit and coupled to the switch unit, the formatter unit configured to receive the plurality of signals in the serial form, and output a plurality of formatted signals including the received plurality of signals.

Abstract: The present disclosure relates generally to systems and methods for direct current (DC) correction in wireless devices. In one example, a method includes setting a cutoff frequency of a filter at a first frequency, where a signal entering the filter is attenuated based on the cutoff frequency. If a qualified change is detected in a DC component of the signal, the cutoff frequency is set at a second frequency that attenuates more of the signal than the first frequency for a defined time period. The cutoff frequency may then be set to the first frequency after the defined time period.

Abstract: A CORDIC circuit capable of performing precise vector rotation, including a pre-rotation stage configured to selectively rotate an input vector by 90 degrees and to produce a pre-rotated vector. A first stage is configured to perform a first set of iterative CORDIC calculations on the pre-rotated vector and to produce a first rotated vector and a remaining rotation value. A second stage configured to perform a second set of iterative CORDIC calculations on the first rotated vector and to produce a second rotated vector, the second rotated vector corresponding to the input vector.

Abstract: A method and system for verifying the design of an integrated circuit including an analog portion and a digital portion are disclosed. As one example, a method for verifying the design of an integrated circuit is disclosed, which includes the steps of generating an analog stimulus, performing a simulation test of the analog portion of the integrated circuit using the analog stimulus as an input, collecting data at an output of the analog portion of the integrated circuit, generating a digital stimulus with the collected data, performing a simulation test of the digital portion of the integrated circuit using the digital stimulus as an input, validating data at an output of the digital portion of the integrated circuit, regression testing the digital portion of the integrated circuit using the digital stimulus as an input, and comparing a result of the regression testing step with a result of the validating data step.

Abstract: The present disclosure relates generally to systems and methods for direct current (DC) correction in wireless devices. In one example, a method includes setting a cutoff frequency of a filter at a first frequency, where a signal entering the filter is attenuated based on the cutoff frequency. If a qualified change is detected in a DC component of the signal, the cutoff frequency is set at a second frequency that attenuates more of the signal than the first frequency for a defined time period. The cutoff frequency may then be set to the first frequency after the defined time period.

Abstract: A reconfiguration unit capable of switching between multiple programmable modes of operation, said electronic device including a first set of programmable registers storing configuration data corresponding to a first mode of operation; a second set of programmable registers storing configuration data corresponding to a second mode of operation; a plurality of multiplexers each connecting corresponding ones of the first and second set of programmable registers with a respective one of a plurality of configurable processing block; and a mode register connected to the plurality of multiplexers to selectively connect the first set of programmable registers or the second set of programmable registers to the plurality of configurable processing blocks. Also described is a related wireless mobile station and configuration method.

Abstract: The present disclosure relates generally to systems and methods for tuning power consumption and group delay in circuits such as radio frequency integrated circuits (RFICs). In one example, a system includes first and second gating blocks configured to reduce a first clock signal operating at a first clock rate to a second clock rate and a third clock rate, respectively. A first processing block coupled to the first gating block operates at the second clock rate. A second processing block is coupled to the first processing block and the second gating block, and operates at the third clock rate. The first processing block changes a flag state from a first state to a second state when transmitting a first data sample to the second processing block, and changes the flag state from the second state to the first state when transmitting a second data sample to the second processing block.

Abstract: Apparatus and method for regulating data in a signal processing pipeline are disclosed. For example, an apparatus is disclosed that includes a first element operable to determine a time interval between a first plurality of data samples input to the signal processing pipeline, and calculate a sample spacing count value associated with the time interval, a second element coupled to the first element, the second element operable to hold the sample spacing count value until the time interval between the first plurality of data samples is changed, a third element coupled to the second element and the signal processing pipeline, the third element operable to output a control signal to the signal processing pipeline, and responsive to the control signal, the signal processing pipeline operable to output a second plurality of data samples.