Patents by Inventor William Motsiff

William Motsiff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080064189
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: October 31, 2007
    Publication date: March 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Publication number: 20080026566
    Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
    Type: Application
    Filed: August 30, 2007
    Publication date: January 31, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Gambino, Edward Cooney, Anthony Stamper, William Motsiff, Michael Lane, Andrew Simon
  • Publication number: 20070275565
    Abstract: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc.
    Type: Application
    Filed: August 15, 2007
    Publication date: November 29, 2007
    Inventors: Edward Cooney, Robert Geffken, Vincent McGahay, William Motsiff, Mark Murray, Amanda Piper, Anthony Stamper, David Thomas, Elizabeth Webster
  • Publication number: 20070018280
    Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
    Type: Application
    Filed: September 26, 2006
    Publication date: January 25, 2007
    Inventors: William Motsiff, William Tonti, Richard Williams
  • Publication number: 20060246682
    Abstract: A method of integrating circuit components under bond pads includes establishing a trench border on a circuit element and synthesizing a set of trench mesh edges of a trench mesh to be coincident with the trench border on the circuit element. The method further includes eliminating a trench mesh contained within the trench border of the trench circuit element.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ephrem Gebreselasie, William Motsiff, Wolfgang Sauter, Steven Voldman
  • Publication number: 20060202302
    Abstract: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.
    Type: Application
    Filed: May 5, 2006
    Publication date: September 14, 2006
    Applicant: International Business Machines Corporation
    Inventors: Robert Geffken, William Motsiff
  • Publication number: 20060145291
    Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.
    Type: Application
    Filed: February 27, 2006
    Publication date: July 6, 2006
    Applicant: International Business Machines Corporation
    Inventors: Dinesh Badami, Tom Lee, Baozhen Li, Gerald Matusiewicz, William Motsiff, Christopher Muzzy, Kimball Watson, Jean Wynne
  • Publication number: 20060099775
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: December 22, 2005
    Publication date: May 11, 2006
    Applicant: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Publication number: 20050245098
    Abstract: A method for selectively altering dielectric properties of a semi-conductor device. In an exemplary embodiment, the method includes applying energy to a local region of interest, the local region of interest including a thermally alterable dielectric such that said heating caused by the applied energy causes a dielectric constant of the thermally alterable dielectric to change.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward Cooney, William Motsiff
  • Publication number: 20050245068
    Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.
    Type: Application
    Filed: July 5, 2005
    Publication date: November 3, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey Gambino, Edward Cooney, Anthony Stamper, William Motsiff, Michael Lane, Andrew Simon
  • Publication number: 20050160575
    Abstract: Integration of high performance copper inductors are provided wherein a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal+1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal+1 level. The invention provides methods for integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal+1 wiring. The subject invention uses dielectric deposition, spacer formation, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.
    Type: Application
    Filed: January 22, 2004
    Publication date: July 28, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Gambino, William Motsiff, Erick Walton
  • Publication number: 20050101114
    Abstract: Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.
    Type: Application
    Filed: September 30, 2003
    Publication date: May 12, 2005
    Inventors: Timothy Daubenspeck, Thomas McDevitt, William Motsiff, Anthony Stamper
  • Publication number: 20050093091
    Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 5, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Badami, Tom Lee, Baozhen Li, Gerald Matusiewicz, William Motsiff, Christopher Muzzy, Kimball Watson, Jean Wynne
  • Publication number: 20050077593
    Abstract: A structure and associated method for protecting an electrical structure during a fuse link deletion by focused radiation. The structure comprises a fuse element, a protection plate, a first dielectric layer, and a second dielectric layer. The structure is formed within a semiconductor device. The protection plate is formed within the first dielectric layer using a damascene process. The second dielectric layer is formed over the protection plate and the first dielectric layer. The fuse element is formed over the second dielectric layer. The fuse element is adapted to be cut with a laser beam. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The protection plate is adapted to shield the first dielectric layer from energy from the laser beam.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 14, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Motsiff, Christopher Muzzy
  • Publication number: 20050067673
    Abstract: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Geffken, William Motsiff
  • Publication number: 20050051868
    Abstract: A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
    Type: Application
    Filed: October 22, 2004
    Publication date: March 10, 2005
    Inventors: William Motsiff, William Tonti, Richard Williams
  • Publication number: 20050026397
    Abstract: A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Daubenspeck, Jeffrey Gambino, Stephen Luce, Thomas McDevitt, William Motsiff, Mark Pouliot, Jennifer Robbins
  • Patent number: 6426557
    Abstract: A controlled collapse chip connection (C4) structure having stronger resistance to failure is constructed for use with integrated circuit devices having copper wiring. Failure resistance is obtained by replacing the mechanically weak final passivation to copper interface. The weak interface is eliminated by use of a specific peg on peg structure together with a layer of shunt metal having excellent adhesion and barrier characteristics. A shunt metal, e.g., Ta or TaN, is placed between both the copper and final passivation and the copper and C4 metals such that it overlaps the edge of the peg defined wiring mesh to encase the copper. Overlap is obtained by the peg on peg structure where a SiO2 peg defines the copper wire mesh and a smaller Si3N4 peg placed on the SiO2 peg defines the overlap above the mesh wire and provides the ability to pattern the overlayer shunt without exposure of the copper conductor.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Timothy Daubenspeck, Stephen E. Luce, William Motsiff