Patents by Inventor William N. Eatherton
William N. Eatherton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7899067Abstract: Methods and apparatus are disclosed for generating and using an enhanced tree bitmap data structure in determining a longest prefix match, such as in a router, packet switching system. One implementation organizes the tree bitmap to minimize the number of internal nodes that must be accessed during a lookup operation. A pointer is included in each of the trie or search nodes to the best match so far entry in the leaf or results array which allows direct access to this result without having to parse a corresponding internal node. Moreover, one implementation stores the internal node for a particular level as a first element in its child array. Additionally, one implementation uses a general purpose lookup engine that can traverse multiple tree bitmaps or other data structures simultaneously, and perform complete searches, partial searches, and resume partial searches such as after receiving additional data on which to search.Type: GrantFiled: May 31, 2002Date of Patent: March 1, 2011Assignee: Cisco Technology, Inc.Inventors: Vijay Rangarajan, Dalit Sagi, William N. Eatherton
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Patent number: 7613134Abstract: Methods and apparatus are disclosed for storing tree data structures among and within multiple memory channels, which may be of particular use with, but not limited to tree bitmap data structures. A subtree (or entire tree) typically includes one or more leaf arrays and multiple tree arrays. One or more leaf arrays are typically stored in a first set of memory channels of N+1 sets of memory channels, the N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels. Each of N contiguous levels of the multiple tree arrays are stored in a different one of said N sets of memory channels, wherein each of the multiple tree arrays at a same level of said N contiguous levels is stored in the same memory channel set of said N sets of memory channels. A memory channel for storing a particular level is typically assigned based on one or more current occupancy levels of the memory channels.Type: GrantFiled: March 31, 2008Date of Patent: November 3, 2009Assignee: Cisco Technology, Inc.Inventors: Vijay Rangarajan, Shyamsundar N. Maniyar, William N. Eatherton
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Patent number: 7496035Abstract: Methods and apparatus are disclosed for defining flow types and instances thereof such as for identifying packets corresponding to instances of the flow types. A flow type is defined and includes a set of properties including at least one of the possible properties selectable when defining a flow type. An instance of the flow type is defined and a set of corresponding associative memory entries is generated. A lookup word generator of a packet processing engine is typically notified of the use of the flow type, and one or more lookup words are generated typically by extracting fields from a received packet and/or from other sources. Based on a result of lookup operations on the set of associative memories entries using the generated one or more lookup words, the received packet can be identified as whether it matches or does not match the instance of the flow type.Type: GrantFiled: January 31, 2003Date of Patent: February 24, 2009Assignee: Cisco Technology, Inc.Inventors: Ganesh Sadasivan, Rengabashyam Srinivas, William N. Eatherton, Xiaoxue Ma, Peram Marimuthu
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Publication number: 20080181139Abstract: Methods and apparatus are disclosed for storing tree data structures among and within multiple memory channels, which may be of particular use with, but not limited to tree bitmap data structures. A subtree (or entire tree) typically includes one or more leaf arrays and multiple tree arrays. One or more leaf arrays are typically stored in a first set of memory channels of N+1 sets of memory channels, the N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels. Each of N contiguous levels of the multiple tree arrays are stored in a different one of said N sets of memory channels, wherein each of the multiple tree arrays at a same level of said N contiguous levels is stored in the same memory channel set of said N sets of memory channels. A memory channel for storing a particular level is typically assigned based on one or more current occupancy levels of the memory channels.Type: ApplicationFiled: March 31, 2008Publication date: July 31, 2008Applicant: Cisco Technology, Inc., a corporation of CaliforniaInventors: VIJAY RANGARAJAN, SHYAMSUNDAR N. MANIYAR, WILLIAM N. EATHERTON
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Patent number: 7404015Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques.Type: GrantFiled: August 24, 2002Date of Patent: July 22, 2008Assignee: Cisco Technology, Inc.Inventors: Rami Zemach, Vitaly Sukonik, William N. Eatherton, John H. W. Bettink, Moshe Voloshin
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Patent number: 7352739Abstract: Tree data structures are stored among and within multiple memory channels, which may be of particular use with, but not limited to tree bitmap data structures. A subtree (or entire tree) typically includes one or more leaf arrays and multiple tree arrays. One or more leaf arrays are typically stored in a first set of memory channels of N+1 sets of memory channels, the N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels. Paths of the multiple tree arrays are typically stored in said N memory channels, wherein each tree array of the multiple tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels.Type: GrantFiled: January 31, 2003Date of Patent: April 1, 2008Assignee: Cisco Technology, Inc.Inventors: Vijay Rangarajan, Shyamsundar N. Maniyar, William N. Eatherton
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Patent number: 7349415Abstract: Methods and apparatus are disclosed for generating and using an enhanced tree bitmap data structure in determining a longest prefix match, such as in a router, packet switching system. One implementation organizes the tree bitmap to minimize the number of internal nodes that must be accessed during a lookup operation. A pointer is included in each of the trie or search nodes to the best match so far entry in the leaf or results array which allows direct access to this result without having to parse a corresponding internal node. Moreover, one implementation stores the internal node for a particular level as a first element in its child array. Additionally, one implementation uses a general purpose lookup engine that can traverse multiple tree bitmaps or other data structures simultaneously, and perform complete searches, partial searches, and resume partial searches such as after receiving additional data on which to search.Type: GrantFiled: October 23, 2002Date of Patent: March 25, 2008Assignee: Cisco Technology, Inc.Inventors: Vijay Rangarajan, Dalit Sagi, William N. Eatherton
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Patent number: 7313093Abstract: Methods and apparatus are disclosed for selectively discarding packets such as in, but not limited to a packet switching system, by reacting to packet traffic conditions to reduce or eliminate the indiscriminate discarding of packets during identified overload conditions. Typically, a first element forwards multiple packets to a second element, each of the multiple packets being associated with a packet overload condition type of possible packet overload condition types, including, but not limited to a discard-on-overload type and a retain-on-overload type. The first element forwards a condition indication to the second element. The second element receives the condition indication and a particular packet. The second element discards the particular packet if the received condition indication is associated with the overload state and the packet overload condition type of the particular received packet is associated with the discard-on-overload type.Type: GrantFiled: November 26, 2002Date of Patent: December 25, 2007Assignee: Cisco Technology, Inc.Inventors: William N. Eatherton, John H. W. Bettink
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Patent number: 7304999Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, a packet of multiple streams of packets is received. A subset of bytes of the packet are distributed to the next packet processor determined based on a distribution pattern. The subset of the packet is processed to generate a modified subset, which is gathered in turn based on the distribution pattern; and a modified packet including the modified subset is forwarded.Type: GrantFiled: August 24, 2002Date of Patent: December 4, 2007Assignee: Cisco Technology Inc.Inventors: Vitaly Sukonik, Michael Laor, Michael B. Galles, Moshe Voloshin, William N. Eatherton, Rami Zemach, John H. W. Bettink
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Patent number: 7249149Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for defining, creating and using tree bitmap data structures, such as for, but not limited to their use in performing lookup operations (e.g., longest prefix matching, etc.). The data structure typically includes a tree bitmap for identifying for each node of multiple nodes within a stride of a number of tree levels greater than one whether each node is a prefix or vacant node, the multiple nodes representing multiple tree levels, a lowest level subset of the multiple nodes corresponding to a lowest level of the tree levels in the stride, the lowest level subset of the multiple nodes including two or more nodes. A child bitmap is typically used for identifying which trie paths emanate and which trie paths do not emanate from the lowest level subset of the multiple nodes.Type: GrantFiled: April 26, 2004Date of Patent: July 24, 2007Assignee: Washington UniversityInventors: William N. Eatherton, Zubin D. Dittia
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Patent number: 7237059Abstract: Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on modification mappings, forcing a no-hit condition in response to a highest-priority matching entry including a force no-hit indication, selecting among various sets or banks of associative memory entries in determining a lookup result, and detecting and propagating error conditions. In one implementation, each block retrieves a modification mapping from a local memory and modifies a received search key based on the mapping and received modification data. In one implementation, each of the associative memory entries includes a field for indicating that a successful match on the entry should or should not force a no-hit result. In one implementation, an indication of which associative memory blocks or sets of entries to use in a particular lookup operation is retrieved from a memory.Type: GrantFiled: December 28, 2005Date of Patent: June 26, 2007Assignee: Cisco Technology, IncInventors: William N. Eatherton, Jaushin Lee, Bangalore L. Priyadarshan, Priyank Ramesh Warkhede, Fusun Ertemalp, Hugh Weber Holbrook, Dileep Kumar Devireddy, Bhushan Mangesh Kanekar, Venkateshwar Rao Pullela
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Patent number: 7103708Abstract: Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on modification mappings, forcing a no-hit condition in response to a highest-priority matching entry including a force no-hit indication, selecting among various sets or banks of associative memory entries in determining a lookup result, and detecting and propagating error conditions. In one implementation, each block retrieves a modification mapping from a local memory and modifies a received search key based on the mapping and received modification data. In one implementation, each of the associative memory entries includes a field for indicating that a successful match on the entry should or should not force a no-hit result. In one implementation, an indication of which associative memory blocks or sets of entries to use in a particular lookup operation is retrieved from a memory.Type: GrantFiled: August 10, 2002Date of Patent: September 5, 2006Assignee: Cisco Technology, Inc.Inventors: William N. Eatherton, Jaushin Lee, Bangalore L. Priyadarshan, Priyank Ramesh Warkhede, Fusun Ertemalp, Hugh Weber Holbrook, Dileep Kumar Devireddy, Bhushan Mangesh Kanekar, Venkateshwar Rao Pullela
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Patent number: 7065609Abstract: Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on modification mappings, forcing a no hit condition in response to a highest priority matching entry including a force no hit indication, selecting among various blocks or sets of associative memory entries in determining a lookup result, and detecting and propagating error conditions. In one implementation, indications of which associative memory blocks to use and/or enable in a particular lookup operation are retrieved from one or more memories, such as that based on received a profile ID. In one implementation, which may or may not be in a cascaded configuration, one or more identified or received error conditions are propagated in such a manner as to identify a source of each error condition.Type: GrantFiled: August 10, 2002Date of Patent: June 20, 2006Assignee: Cisco Technology, Inc.Inventors: William N. Eatherton, Jaushin Lee, Bangalore L. Priyadarshan, Priyank Ramesh Warkhede, Fusun Ertemalp
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Patent number: 7028136Abstract: Methods and apparatus are disclosed for, inter alia, managing idle time and performing lookup operations to adapt to refresh requirements and/or operational rates of the particular associative memory or other devices used to implement the system. A system typically a controller coupled to a circuit including includes multiple associative memories. The controller receives performance information from at least one of the associative memories and generates idle time corresponding to the performance information. This performance information may include an actual refresh requirement for each of the associate memories or the worst-case requirement of one of the associative memories, so that the controller can intermittently provide the actual refresh cycles required, if any, by a particular implementation.Type: GrantFiled: January 31, 2003Date of Patent: April 11, 2006Assignee: Cisco Technology, Inc.Inventors: Bangalore L. Priyadarshan, Jaushin Lee, William N. Eatherton
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Patent number: 6990063Abstract: Methods and apparatus are disclosed for distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system. In one embodiment, a packet switching system detects faults and propagates indications of these faults to the input interfaces of a packet switch, so the packet switch can adapt the selection of a route over which to send a particular packet. Faults are identified by various components of the packet switching system and relayed to one or more switching components to generate a broadcast packet destined for all input ports (i.e., to each I/O interface in a packet switch having folded input and output interfaces). Other embodiments, generate one or more multicast or unicast packets. The I/O interface maintains one or more data structures indicating the state of various portions of the packet switching system.Type: GrantFiled: March 7, 2000Date of Patent: January 24, 2006Assignees: Cisco Technology, Inc., Washington UniversityInventors: Daniel E. Lenoski, William N. Eatherton, John Andrew Fingerhut, Jonathan S. Turner
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Patent number: 6775737Abstract: Methods and apparatus are disclosed for allocating and using range identifiers as input values to associative memories, especially binary content-addressable memories (CAMs) and ternary content-addressable memories (TCAMs). In one implementation, each of multiple non-overlapping intervals are identified with one of multiple unique identifiers. An indication of a mapping between the multiple non-overlapping intervals and the multiple unique identifiers is maintained. A particular unique identifier is determined from said multiple unique identifiers based on a value and said multiple non-overlapping intervals. A lookup operation is performed on an associative memory using the particular unique identifier to generate a result. One implementation uses a trie representation of a range tree of the intervals to derive the unique identifiers.Type: GrantFiled: October 9, 2001Date of Patent: August 10, 2004Assignee: Cisco Technology, Inc.Inventors: Priyank Ramesh Warkhede, William N. Eatherton, Shyamsundar N. Maniyar, Peram Marimuthu
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Method and apparatus for reducing the required size of sequence numbers used in resequencing packets
Patent number: 6747972Abstract: In one implementation, a first set of packet switch sequence numbers is used for end-to-end resequencing of packets within a packet switch, and a second set of interconnection network sequence number is used in the resequencing of packets within an interconnection network of the packet switch. A packet switch sequence number is maintained at each input interface of the packet switch for each output interface, while each output interface maintains a packet switch sequence number for each input interface. A corresponding sequence number is added to packets sent between corresponding input-output interface pairs. Similarly, an interconnection network sequence number is maintained at each input port of an interconnection network for each output port, while each output port maintains an interconnection network sequence number for each input port. A corresponding sequence number is added to packets sent between corresponding input-output port pairs.Type: GrantFiled: March 7, 2000Date of Patent: June 8, 2004Assignee: Cisco Technology, Inc.Inventors: Daniel E. Lenoski, William N. Eatherton, Zubin D. Dittia, John Andrew Fingerhut -
Patent number: 6728732Abstract: In random access memory, a data structure of trie elements of compact and fixed size is provided in order to store elements of a hierarchical prefix-type data structure such that the data structure can be searched quickly. A trie element according to the invention contains the data in one stride of the search through the prefix-type data structure. According to the invention, the trie element may contain 1) a description of the tree structure associated with the trie element, 2) a description of the links to the next level trie element, and 3) a pointer to the storage location of the next level trie element. The prefix structure has a first level trie element, and at least one second level trie element.Type: GrantFiled: February 18, 2003Date of Patent: April 27, 2004Assignee: Washington UniversityInventors: William N. Eatherton, Zubin Dittia
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Patent number: 6728211Abstract: Methods and apparatus are also disclosed for responding to received flow control messages indicating a previously congested port is now in a non-congested state. Many different components that have packets to send to a particular output will receive an indication that they are now allowed to send these packets at roughly the same time as the other components. If all components start sending at the same time, then the packet switch might become congested, possibly very quickly. If the packet switch cannot respond and transmit flow control messages to all of these sources fast enough, certain internal buffers could overflow and thus packets might be lost. On implementation causes components to start sending to the destination at varying times to gradually increase the traffic being sent to the destination.Type: GrantFiled: March 7, 2000Date of Patent: April 27, 2004Assignee: Cisco Technology, Inc.Inventors: Vinod Gerard John Peris, Jonathan S. Turner, Zubin D. Dittia, William N. Eatherton
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Publication number: 20040039787Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques.Type: ApplicationFiled: August 24, 2002Publication date: February 26, 2004Inventors: Rami Zemach, Vitaly Sukonik, William N. Eatherton, John H. W. Bettink, Moshe Voloshin