Abstract: Exemplary substrate processing chambers may include a chamber body defining a processing region. The chamber body may include chamber walls. The chambers may include a showerhead disposed atop the chamber body. The chambers may include a susceptor disposed within the chamber body. The support plate may include a substrate receiving surface. A peripheral edge of the susceptor may define a plurality of notches that extend through a thickness of the support plate. The chambers may include a plurality of shadow frame supports extending from the chamber walls. At least some of the plurality of shadow frame supports may include protrusions that extend inward into an interior of the chamber body. Each of the protrusions may be vertically aligned with a respective one of the plurality of notches. The chambers may include a shadow frame that is positionable on the plurality of shadow frame supports.

Abstract: Exemplary substrate processing chambers may include a chamber body defining a processing region. The chambers may include a backing plate disposed atop the chamber body, a diffuser above the processing region and supported by the backing plate, and a cooling frame disposed between the backing plate and the diffuser. The cooling frame may be coupled with the diffuser. The cooling frame may include a body having one or more fluid inlets and one or more fluid outlets. The body may define an opening. The fluid inlets may be in fluid communication with the one or more fluid outlets via one or more fluid lumens that each extend at least partially about a periphery of the opening. The fluid inlets may be in fluid communication with one or more fluid supply lumens. The fluid outlets may be in fluid communication with one or more fluid return lumens.

Abstract: Exemplary diffusers for a substrate processing chamber may include a diffuser body that is characterized by a first surface on an inlet side of the diffuser body and a second surface on an outlet side of the diffuser body. The diffuser body may define a plurality of apertures through a thickness of the diffuser body. The first surface may not be anodized. The second surface may be anodized.

Abstract: Embodiments of the present disclosure relate to a shadow frame support with one or more flow controllers and a method of controlling the flow of gases through the shadow frame support. The shadow frame support includes a body coupled to walls of a chamber such that a top surface of the shadow frame support is horizontally disposed in the chamber. The body has a plurality of channels disposed therethrough. Each channel includes a flow controller. The flow controller may be adjusted in real-time to change the open ratio of the flow controller.

Abstract: Embodiments of the present disclosure relate to a shadow frame support with one or more flow controllers and a method of controlling the flow of gases through the shadow frame support. The shadow frame support includes a body coupled to walls of a chamber such that a top surface of the shadow frame support is horizontally disposed in the chamber. The body has a plurality of channels disposed therethrough. Each channel includes a flow controller. The flow controller may be adjusted in real-time to change the open ratio of the flow controller.

Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

Abstract: A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.