Abstract: A liquid dispensing system for dispensing two or more liquids of different composition, viscosity, solubility and/or miscibility at high filling speeds into a container through a unitary dispensing nozzle to improve homogeneous mixing of such liquids, while said nozzle is an integral piece free of any movable parts.

Abstract: The present disclosure relates to methods, compositions, and kits for concentrating and purifying at least one target analyte from a clinical biological sample. In some embodiments, the methods involve one or more aqueous two-phase system (ATPS) compositions and at least one solid phase medium. Some embodiments provide a kit comprising one or more ATPS compositions, a binding buffer; and a solid phase medium. Other embodiments provide methods of treating cancers or infectious diseases in a patient in need thereof.

Abstract: A liquid dispensing system for dispensing two or more liquids of different composition, viscosity, solubility and/or miscibility at high filling speeds into a container through a unitary dispensing nozzle to improve homogeneous mixing of such liquids, while said nozzle is an integral piece free of any movable parts.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Abstract: Systems, apparatuses, and methods for implemented secure encrypted virtualization are disclosed. In one embodiment, a system includes at least one or more main processors, a memory, a memory controller, and a security processor. The system is configured to detect a request to provision a guest virtual machine (VM) in a secure environment. The system computes a first integrity check value from the guest VM prior to initiating the guest VM. The system initiates the guest VM responsive to receiving an indication that the first integrity check value is valid. The system encrypts, with a first encryption key, the guest VM stored in the memory. The security processor loads the first encryption key into the memory controller, and the memory controller encrypts the guest VM with the first encryption key.

Abstract: The present invention discloses a system and method to recognize the geometric primitives and estimate the intended geometric relationship between the primitives. The system also provides its user an interactive feedback mechanism to better provide the graphic results intended by the user. The areas enclosed by the lines drew by the user is also considered by the system in the graphic result calculation process to improve the graphic results. One main feature of the present system is to provide geometric constraints estimations based on calculation of the constraints' effect on all related primitives and previously existing geometric constraints.

Abstract: The present invention relates to a toy which holds and launches multiple paper airplanes. It utilizes a user input device, such as a trigger or button, to initiate firing. On initiation one or more paper airplanes are advanced into a spinning wheel, which is powered by an electric motor, that accelerates the paper airplanes out of the toy. Upon leaving the toy, the paper airplanes fly through the air to their target.

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

Abstract: The present disclosure discloses a padlock, comprising a lock cylinder and a lock housing. The lock cylinder is rotatable between a lock position and an unlock position with rotation of a key. The a lock housing comprises a sleeve shaped to fit with and for receiving the lock cylinder, a first prong extending outward from the sleeve and having a first recessed portion and a second prong extending outward from the sleeve and having a second recessed portion; wherein when the lock cylinder is rotated into the lock position/the unlock position, the through holes are aligned with the first recessed portion/the second recessed portion, the first pins/second pins are movable in the through holes and the first recessed portion/the second recessed portion, allowing the removal of the key from the keyhole.

Abstract: The present disclosure discloses a padlock, comprising a lock cylinder and a lock housing. The lock cylinder is rotatable between a lock position and an unlock position with rotation of a key. The a lock housing comprises a sleeve shaped to fit with and for receiving the lock cylinder, a first prong extending outward from the sleeve and having a first recessed portion and a second prong extending outward from the sleeve and having a second recessed portion; wherein when the lock cylinder is rotated into the lock position/the unlock position, the through holes are aligned with the first recessed portion/the second recessed portion, the first pins/second pins are movable in the through holes and the first recessed portion/the second recessed portion, allowing the removal of the key from the keyhole.

Abstract: The present invention discloses a padlock, comprising a lock cylinder rotatable between a lock position and an unlock position with rotation of a key. The lock cylinder comprises a keyhole, at least one first through hole extending along a first direction for housing at least one first pin, and at least one second through hole extending along a second direction for housing at least one second pin. When the key is in the keyhole, the teeth of the key are aligned with the at least one first pin and the at least one indentations are aligned with the at least one second pin, allowing the lock cylinder to rotate between the lock position and the unlock position with rotation of the key.

Abstract: The present invention discloses a padlock, comprising a lock cylinder rotatable between a lock position and an unlock position with rotation of a key. The lock cylinder comprises a keyhole, at least one first through hole extending along a first direction for housing at least one first pin, and at least one second through hole extending along a second direction for housing at least one second pin. When the key is in the keyhole, the teeth of the key are aligned with the at least one first pin and the at least one indentations are aligned with the at least one second pin, allowing the lock cylinder to rotate between the lock position and the unlock position with rotation of the key.

Abstract: The present invention discloses a system and method to recognize the geometric primitives and estimate the intended geometric relationship between the primitives. The system also provides its user an interactive feedback mechanism to better provide the graphic results intended by the user. The areas enclosed by the lines drew by the user is also considered by the system in the graphic result calculation process to improve the graphic results. One main feature of the present system is to provide geometric constraints estimations based on calculation of the constraints' effect on all related primitives and previously existing geometric constraints.

Abstract: In an analysis of a semiconductor device under test (DUT) using a Thermal Induced Voltage Alteration (TIVA) tool, the TIVA is connected to an output of the DUT and the DC component on the output is decoupled from the TIVA. The remaining AC component from the output is analyzed by the TIVA while scanning the DUT with a scanning laser to identify locations on the DUT that produce signal anomalies at the DUT output.