Abstract: A method and apparatus for controlling current flow in current sources includes a current source FET (18), a control FET (20), and a driver circuit which includes complementary logic (310). The use of complementary logic for control advantageausly allows commonly available logic functions to control the current flow in individual current sources while maintaining a substantially constant bias voltage on the gate of the current source FETs. A chip-wide bias generator can be maintained substantially constant while controlling individual current sources.

Abstract: A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).