Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

Abstract: A data transmission system employs a method of aligning transmission lanes with reception lanes in a multiplexing arrangement. A plurality of control symbols and lane identifiers are transmitted on each of the transmission lanes. The transmission lanes are divided into groups for time-division multiplexing. Within the groups, the transmission lanes are time-division multiplexed and then wave-division multiplexed onto a data link. Upon reception, wave-division and time-division demultiplexing is conducted to extract groups of reception lanes corresponding to the groups of transmission lanes. One of the reception lanes in each group of reception lanes is monitored for receipt of a control symbol followed by a lane identifier. Upon receipt, the lane assignment of the reception lanes is rotated within the particular group if the received lane identifier does not match the identity of the reception lane being monitored.

Abstract: A technique for training links in a computing system is disclosed. In one aspect, the technique includes configuring a first receiver in a first port using a first training sequence or a second training sequence; transmitting the second training sequence from the first port indicating the first receiver is configured; and receiving a second training sequence transmitted by a second port at the first port, the second training sequence transmitted by the second port indicating that a second receiver in the second port is configured. In a second aspect, the technique includes locking a communication link; handshaking across the locked link to indicate readiness for data transmission; transmitting information after handshaking across the locked link.

Abstract: A data transmission system uses a method of aligning a plurality of transmission lanes with a plurality of reception lanes in a time-division multiplexing arrangement. The method utilizes a plurality of control symbols and lane identifiers that are transmitted on each of the transmission lanes during link initialization and training. The control symbols and lane identifiers are time-division multiplexed onto a data link and subsequently demultiplexed onto the plurality of reception lanes. One of the reception lanes is monitored for receipt of a control symbol followed by a lane identifier. Upon receipt, a lane identifier is compared to the identity of the reception lane being monitored. If the received lane identifier does not match the identity of the reception lane being monitored, the assignment of the reception lanes is rotated.

Abstract: A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver.

Abstract: Adaptive sets of lanes are configured between routers in a system area network. Source nodes determine whether packets may be adaptively routed between the lanes by encoding adaptive control bits in the packet header. The adaptive control bits also facilitate the flushing of all lanes of the adaptive set. Adaptive sets may also be used in uplinks between levels of a fat tree.

Abstract: A computer system includes a primary processor and a secondary processor running in lockstep. The lockstep may or may not be synchronous. Errors occurring in the primary processor or the secondary processor are reported to an error-handling module. If the error is a recoverable error, the state of one of the processors is saved and the processors are restarted using the saved state. In addition to the reporting of errors from the processors, cross checking of the operation of the processors is performed to detect a divergence in the operation of the processors. If the divergence is reported to be due to a recoverable error, the state of the one of the processors is saved and the processors are restarted using the saved state. Procedures are also disclosed to ensure that data corruption does not propagate onto an associated network, and to ensure that the system is not lost as a network resource during processor restart.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A link extender node is used to extend links between end nodes and/or routing nodes in a system area network. A connection includes a first link, coupling an end or routing node to a local port of a first link extender, a second link coupling the remote ports of first and second link extenders, and a third link coupling the local port of the second link extender to an end or routing node. The link extender includes link exception detection logic and transmits a this link bad command on the link generating the exception and transmits an other link bad command on the link not generating the exception.

Abstract: An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A link extender is used for extending links between end nodes or router nodes in a system area network. Nodes in the network transmit link alive symbols to indicate that a link is alive. The link extender includes a link alive propagation feature for propagating the loss of link alive between ports of the link extender.

Abstract: A multiprocessor or clustered system with processing elements communicatively interconnected transmits and receives data in the form of message packets. Certain of the message packets are either responding to earlier requests with the data, or are requests that the data of the packet be written at the destination. Each message packet has an initial portion that includes information about the packet, including what the data is carrying (i.e., data in response to an earlier request, or data to be written), the source and ultimate destination of the message packet. This information prevents errant data being written at the destination by determining if the source has “permission” to send such data to the destination. When a message packet carrying data is received, processing of the packet is started in parallel with continued reception of the data it carries by using the information contained in the initial portion to check the permissions.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed herein. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device Initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol groups” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from buffers having start symbols is temporarily suspended.

Abstract: A data transmission system employs a method of aligning transmission lanes with reception lanes in a multiplexing arrangement. A plurality of control symbols and lane identifiers are transmitted on each of the transmission lanes. The transmission lanes are divided into groups for time-division multiplexing. Within the groups, the transmission lanes are time-division multiplexed and then wave-division multiplexed onto a data link. Upon reception, wave-division and time-division demultiplexing is conducted to extract groups of reception lanes corresponding to the groups of transmission lanes. One of the reception lanes in each group of reception lanes is monitored for receipt of a control symbol followed by a lane identifier. Upon receipt, the lane assignment of the reception lanes is rotated within the particular group if the received lane identifier does not match the identity of the reception lane being monitored.

Abstract: A data transmission system uses a method of aligning a plurality of transmission lanes with a plurality of reception lanes in a time-division multiplexing arrangement. The method utilizes a plurality of control symbols and lane identifiers that are transmitted on each of the transmission lanes during link initialization and training. The control symbols and lane identifiers are time-division multiplexed onto a data link and subsequently demultiplexed onto the plurality of reception lanes. One of the reception lanes is monitored for receipt of a control symbol followed by a lane identifier. Upon receipt, a lane identifier is compared to the identity of the reception lane being monitored. If the received lane identifier does not match the identity of the reception lane being monitored, the assignment of the reception lanes is rotated.

Abstract: A computer system includes a primary processor and a secondary processor running in lockstep. The lockstep may or may not be synchronous. Errors occurring in the primary processor or the secondary processor are reported to an error-handling module. If the error is a recoverable error, the state of one of the processors is saved and the processors are restarted using the saved state. In addition to the reporting of errors from the processors, cross checking of the operation of the processors is performed to detect a divergence in the operation of the processors. If the divergence is reported to be due to a recoverable error, the state of the one of the processors is saved and the processors are restarted using the saved state. Procedures are also disclosed to ensure that data corruption does not propagate onto an associated network, and to ensure that the system is not lost as a network resource during processor restart.

Abstract: An apparatus and method for multi-threaded transaction status management tracks elapsed time from the receipt of multiple independent transaction requests utilizing a unique transaction number included in the descriptor of a longer than a predetermined time are invalidated. The transaction number is also used as an index to stored authentication information and the transaction number is included in a response header and is used to access the stored information to authenticate the response.