Abstract: A semiconductor device includes an emitter region, a contact region, and a resistive medium. The resistive medium is connected between the contact region and the emitter region. The contact region and the emitter region each include an edge facing each other. At least a portion of the emitter region edge and at least a portion of the contact region edge are non-parallel relative to each other. This configuration enables an emitter ballast resistance to be provided with varied emitter current flow along the injecting edge of the emitter. Furthermore, by including an additional contact and an additional resistive medium between the contacts, the ballast resistance of the semiconductor device can be increased without decreasing the figure of merit of the device.

Abstract: A very deep P.sup.+ diffusion step is performed prior to the definition of a self-aligning emitter/P.sup.+ region. Furthermore, the initial P.sup.+ region is formed with dimensions sufficiently narrow to allow the subsequent emitter/P.sup.+ formation step to overlap the deeper P.sup.+ step by enough distance for the P.sup.+ step to completely cover the deep P.sup.+ region with its significant lateral diffusion. In this manner, a low sheet resistance in combination with proper alignment of the P.sup.+ heavy region with the emitter region is obtained.

Abstract: The ballast resistance of a semiconductor device is increased without decreasing the figure of merit of the device. The semiconductor device includes an emitter feeder, a first contact coupled to the emitter feeder, a second contact, a resistive medium connected between the first contact and the second contact, an emitter, and a further resistive medium connected between the second contact and the emitter. The ballast resistance of the semiconductor device is increased without decreasing the figure of merit of the device by increasing the distance between the first contact and the second contact.

Abstract: According to the present invention, using an emitter-P.sup.+ (E-P) mask, a low resistance, high conductivity P.sup.+ region of a self-aligned bipolar transistor device is formed prior to the formation of a base region. The P.sup.+ diffusion and drive can thus be accomplished without concern for adverse effects on the base region of the bipolar transistor device, which is yet to be formed. After the P+ diffusion and drive step, the emitter of the bipolar transistor device is uncovered and a base mask used to allow a base implant step. A high base implant energy of approximately 35 to 40 KEV is used to completely penetrate the E-P mask layers, thereby providing a usable, linked base region in the active areas of the bipolar transistor device.

Abstract: Using a silicon etched technique to remove an implanted base and emitter surrounding emitter-base islands, a "mesa" emitter structure can be formed. Using the structure, a self aligned P+ can be formed around emitter-base islands.

Abstract: A semiconductor device is manufactured with precisely formed base and emitter regions. This is accomplished by arranging a plurality of insulator layer portions to form a plurality of windows. A dopant is then applied to the semiconductor device between the windows in order to accurately position emitter regions relative to base regions. In this manner a base of controlled dimensions can be formed. Thus the parasitic resistance of the base can be reduced and the figure of merit (emitter periphery/base area) can be increased.