Patents by Inventor William P. Ingram, III

William P. Ingram, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating antifuses in an integrated circuit device and resulting structure
    Patent number: 5670419
    Abstract: Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 23, 1997
    Assignee: Crosspoint Solutions, Inc.
    Inventors: Pankaj Dixit, William P. Ingram, III, Monta R. Holzworth, Richard Klein
  • Method of fabricating antifuses in an integrated circuit device and resulting structure
    Patent number: 5527745
    Abstract: Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: June 18, 1996
    Assignee: Crosspoint Solutions, Inc.
    Inventors: Pankaj Dixit, William P. Ingram, III, Monta R. Holzworth, Richard Klein
  • Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof
    Patent number: 5493147
    Abstract: An antifuse structure particularly suitable for field programmable gate arrays is presented. In most present day processes the antifuse structure is formed with a refractory metal layer, amorphous silicon layer and refractory metal layer sandwiched between two metal interconnection lines. Unprogrammed resistances of very high values, programmed resistances of very low values, short programming times and desirable programming voltages are among the advantages realized.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: February 20, 1996
    Assignee: Crosspoint Solutions, Inc.
    Inventors: Monta R. Holzworth, Richard Klein, Pankaj Dixit, William P. Ingram, III
  • Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof
    Patent number: 5384481
    Abstract: An antifuse structure particularly suitable for field programmable gate arrays is presented. In most present day processes the antifuse structure is formed with a refractory metal layer, amorphous silicon layer and refractory metal layer sandwiched between two metal interconnection lines. Unprogrammed resistances of very high values, programmed resistances of very low values, short programming times and desirable programming voltages are among the advantages realized.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: January 24, 1995
    Assignee: Crosspoint Solutions, Inc.
    Inventors: Monta R. Holzworth, Richard Klein, Pankaj Dixit, William P. Ingram, III
  • Improved method of fabricating antifuses in an integrated circuit device and resulting structure
    Patent number: 5322812
    Abstract: Various improvements in the fabrication of an antifuse having silicon-amorphous silicon-metal layer structure are presented. Included are improved deposition techniques for the amorphous silicon layer. The improvements include steps for the fabrication of such an antifuse without the use of platinum and the resulting antifuse and contact structures.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: June 21, 1994
    Assignee: Crosspoint Solutions, Inc.
    Inventors: Pankaj Dixit, William P. Ingram, III, Monta R. Holzworth, Richard Klein
  • Plug contact with antifuse
    Patent number: 5233217
    Abstract: An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it.
    Type: Grant
    Filed: May 3, 1991
    Date of Patent: August 3, 1993
    Assignee: Crosspoint Solutions
    Inventors: Pankaj Dixit, Monta R. Holzworth, Richard Klein, William P. Ingram, III