Patents by Inventor William P. Pinello

William P. Pinello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit packages with sandwiched capacitors
    Patent number: 7133294
    Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Priyavadan R. Patel, Chee-Yee Chung, David G. Figueroa, Robert L. Sankman, Yuan-Liang Li, Hong Xie, William P. Pinello
  • Electronic assembly with sandwiched capacitors and methods of manufacture
    Patent number: 6900991
    Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: May 31, 2005
    Assignee: Intel Corporation
    Inventors: Priyavadan R. Patel, Chee-Yee Chung, David G. Figueroa, Robert L. Sankman, Yuan-Liang Li, Hong Xie, William P. Pinello
  • Electronic assembly with sandwiched capacitors and methods of manufacture
    Publication number: 20030102555
    Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Application
    Filed: December 3, 2001
    Publication date: June 5, 2003
    Applicant: Intel Corporation
    Inventors: P. R. Patel, Chee-Yee Chung, Daivd G. Figueroa, Robert L. Sankman, Yuan-Liang Li, Hong Xie, William P. Pinello