Patents by Inventor William Panos

William Panos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940515
    Abstract: A system, method, and computer-readable medium for evaluating structural integrity of a gradient coil disposed in a magnetic resonance imaging system is provided. A sensor obtains a parameter reading of the gradient coil, wherein the parameter reading includes a back electromotive force (back EMF) measurement. The structural integrity of the gradient coil is determined as function of the back EMF measurement.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 26, 2024
    Assignee: GE PRECISION HEALTHCARE LLC
    Inventors: Garrett William Astary, Derek Seeber, Andrew John Panos
  • Patent number: 7249337
    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. According to one embodiment of the present invention, the method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. In certain embodiments, the process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: July 24, 2007
    Assignee: Sanmina-SCI Corporation
    Inventors: Franz Gisin, William Panos, Mahamud Khandokar
  • Publication number: 20040176938
    Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. The method may involve the use of the S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis may be performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the subcircuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Applicant: Sanmina-SCI Corporation
    Inventors: Franz Gisin, William Panos, Mahamud Khandokar