Patents by Inventor William Patrick Delaney

William Patrick Delaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10798207
    Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: October 6, 2020
    Assignee: NETAPP, INC.
    Inventors: Sai Rama Krishna Susarla, Scott Hubbard, William Patrick Delaney, Rodney A. Dekoning
  • Patent number: 10339017
    Abstract: Methods and systems for storing data at a storage device of a storage system are provided. The data is first temporarily stored at a first write cache and an input/output request for a persistence storage device used as a second write cache is generated, when an I/O request size including the received data has reached a threshold value. The data from the first cache is transferred to the persistence storage device and a recovery control block with a location of the data stored at the persistence storage device is updated. An entry is added to a linked list that is used to track valid data stored at the persistence storage device and then the data is transferred from the persistence storage device to the storage device of the storage system.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 2, 2019
    Assignee: NETAPP, INC.
    Inventors: William Patrick Delaney, Joseph Russell Blount, Rodney A. DeKoning
  • Publication number: 20180176323
    Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 21, 2018
    Inventors: Sai Rama Krishna Susarla, Scott Hubbard, William Patrick Delaney, Rodney A. Dekoning
  • Patent number: 9930133
    Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 27, 2018
    Assignee: NetApp, Inc.
    Inventors: Sai Rama Krishna Susarla, Scott Hubbard, William Patrick Delaney, Rodney A. Dekoning
  • Publication number: 20170091054
    Abstract: Methods and systems for storing data at a storage device of a storage system are provided. The data is first temporarily stored at a first write cache and an input/output request for a persistence storage device used as a second write cache is generated, when an I/O request size including the received data has reached a threshold value. The data from the first cache is transferred to the persistence storage device and a recovery control block with a location of the data stored at the persistence storage device is updated. An entry is added to a linked list that is used to track valid data stored at the persistence storage device and then the data is transferred from the persistence storage device to the storage device of the storage system.
    Type: Application
    Filed: November 7, 2016
    Publication date: March 30, 2017
    Inventors: William Patrick Delaney, Joseph Russell Blount, Rodney A. DeKoning
  • Patent number: 9501420
    Abstract: A system and method for recognizing data access patterns in large data sets and for preloading a cache based on the recognized patterns is provided. In some embodiments, the method includes receiving a data transaction directed to an address space and recording the data transaction in a first set of counters and in a second set of counters. The first set of counters divides the address space into address ranges of a first size, whereas the second set of counters divides the address space into address ranges of a second size that is different from the first size. One of a storage device or a cache thereof is selected to service the data transaction based on the first set of counters, and data is preloaded into the cache based on the second set of counters.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: November 22, 2016
    Assignee: NETAPP, INC.
    Inventors: Sai Rama Krishna Susarla, Sandeep Kumar Reddy Ummadi, William Patrick Delaney
  • Patent number: 9489149
    Abstract: Methods and systems for storing data at a storage device of a storage system are provided. The data is first temporarily stored at a first write cache and an input/output request for a persistence storage device used as a second write cache is generated, when an I/O request size including the received data has reached a threshold value. The data from the first cache is transferred to the persistence storage device and a recovery control block with a location of the data stored at the persistence storage device is updated. An entry is added to a linked list that is used to track valid data stored at the persistence storage device and then the data is transferred from the persistence storage device to the storage device of the storage system.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: November 8, 2016
    Assignee: NETAPP, INC.
    Inventors: William Patrick Delaney, Joseph Russell Blount, Rodney A. DeKoning
  • Publication number: 20160117254
    Abstract: A system and method for recognizing data access patterns in large data sets and for preloading a cache based on the recognized patterns is provided. In some embodiments, the method includes receiving a data transaction directed to an address space and recording the data transaction in a first set of counters and in a second set of counters. The first set of counters divides the address space into address ranges of a first size, whereas the second set of counters divides the address space into address ranges of a second size that is different from the first size. One of a storage device or a cache thereof is selected to service the data transaction based on the first set of counters, and data is preloaded into the cache based on the second set of counters.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 28, 2016
    Inventors: Sai Rama Krishna Susarla, Sandeep Kumar Reddy Ummadi, William Patrick Delaney
  • Publication number: 20160119443
    Abstract: A system and method for managing application performance includes a storage controller including a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of managing application performance and a processor coupled to the memory. The processor is configured to execute the machine executable code to receive storage requests from a plurality of first applications via a network interface, manage QoS settings for the storage controller and the first applications, and in response to receiving an accelerate command associated with a second application from the first applications, increase a first share of a storage resource allocated to the second application, decrease unlocked second shares of the storage resource of the first applications, and lock the first share. The storage resource is a request queue or a first cache. In some embodiments, the second application is a throughput application or a latency application.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 28, 2016
    Inventors: Sai Rama Krishna Susarla, Scott Hubbard, William Patrick Delaney, Rodney A. Dekoning
  • Publication number: 20150363285
    Abstract: Methods and systems for storing data at a storage device of a storage system are provided. The data is first temporarily stored at a first write cache and an input/output request for a persistence storage device used as a second write cache is generated, when an I/O request size including the received data has reached a threshold value. The data from the first cache is transferred to the persistence storage device and a recovery control block with a location of the data stored at the persistence storage device is updated. An entry is added to a linked list that is used to track valid data stored at the persistence storage device and then the data is transferred from the persistence storage device to the storage device of the storage system.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Inventors: William Patrick Delaney, Joseph Russell Blount, Rodney A. DeKoning
  • Patent number: 9052834
    Abstract: Disclosed is a storage system architecture. An Environmental service module (ESM) is coupled to one or more array controllers. The ESM is configured with a central processing unit and one or more assist functions. The assist functions may include nonvolatile memory. This nonvolatile memory may be used for write caching, mirroring data, and/or configuration data. The assist functions, or the ESM, may be controlled by the array controllers using SCSI or RDMA commands.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 9, 2015
    Assignee: NetApp, Inc.
    Inventors: Rodney A. DeKoning, Bret S. Weber, William Patrick Delaney, Kenneth F. Day
  • Patent number: 8898380
    Abstract: Disclosed is a RAID data checking system. I/O controllers to read data RAID data from the storage devices and transfer that data to virtual memory address ranges. The P+Q checking function receives the data sent to the virtual memory address ranges. However, instead of storing the incoming data, the P+Q checking function updates intermediate values of the P and Q redundant data calculations associated with the incoming data. When all of the strips have been received, the P+Q checking function will have completed the calculation of P and Q redundant data. In this case, after all the strips and the P or Q data have been received, the P+Q checking function will hold zeroes if all the data and the P and Q data was correct and hold non-zero values if there was an error.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventor: William Patrick Delaney
  • Publication number: 20140040549
    Abstract: Disclosed is a storage system architecture. An Environmental service module (ESM) is coupled to one or more array controllers. The ESM is configured with a central processing unit and one or more assist functions. The assist functions may include nonvolatile memory. This nonvolatile memory may be used for write caching, mirroring data, and/or configuration data. The assist functions, or the ESM, may be controlled by the array controllers using SCSI or RDMA commands.
    Type: Application
    Filed: October 24, 2013
    Publication date: February 6, 2014
    Applicant: NetApp, Inc.
    Inventors: Rodney A. DeKoning, Bret S. Weber, William Patrick Delaney, Kenneth F. Day
  • Patent number: 8595397
    Abstract: Disclosed is a storage system architecture. An Environmental service module (ESM) is coupled to one or more array controllers. The ESM is configured with a central processing unit and one or more assist functions. The assist functions may include nonvolatile memory. This nonvolatile memory may be used for write caching, mirroring data, and/or configuration data. The assist functions, or the ESM, may be controlled by the array controllers using SCSI or RDMA commands.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 26, 2013
    Assignee: Netapp, Inc
    Inventors: Rodney A. DeKoning, Bret S. Weber, William Patrick Delaney, Kenneth F. Day
  • Patent number: 8255676
    Abstract: A non-disruptive method for updating firmware in a first controller 210 of a redundant controller 200 in a storage subsystem 120 is disclosed. This updating occurs while the storage subsystem 120 presents data to a host system 130 in response to a host request 132. During the non-disruptive updating, the updating first controller 210 redirects the host request 132 for data, e.g., drive-A volume 252 normally owned by the first controller 210, to second controller 220 of the redundant controller 200. After the second controller 220 obtains data 134 identified in the host request 132, the operating second controller 220 transfers the data 134 to the updating first controller 210 via an inter-controller channel 202. Once the updating first controller 210 receives the data 134, the first controller 210 presents the data 134 to the host system 130. The host system 130 does not detect that the first controller 210 is updating because the updating process is invisible to the host system 130.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: August 28, 2012
    Assignee: Netapp, Inc.
    Inventors: William Patrick Delaney, Kenneth F. Day
  • Publication number: 20110264857
    Abstract: Disclosed is a RAID data checking system. I/O controllers to read data RAID data from the storage devices and transfer that data to virtual memory address ranges. The P+Q checking function receives the data sent to the virtual memory address ranges. However, instead of storing the incoming data, the P+Q checking function updates intermediate values of the P and Q redundant data calculations associated with the incoming data. When all of the strips have been received, the P+Q checking function will have completed the calculation of P and Q redundant data. In this case, after all the strips and the P or Q data have been received, the P+Q checking function will hold zeroes if all the data and the P and Q data was correct and hold non-zero values if there was an error.
    Type: Application
    Filed: January 9, 2009
    Publication date: October 27, 2011
    Inventor: William Patrick Delaney
  • Publication number: 20100312964
    Abstract: Disclosed is a storage array system. N array controllers are configured with at least two interconnect fabric ports, where N is an integer greater than two. A JBOD unit is configured with at least two interconnect fabric switches. The two interconnect fabric switches each have at least N interconnect fabric ports. Each of the least N of the interconnect fabric ports are directly connected to a corresponding one of the N array controllers, thereby establishing direct redundant connectivity between each of the N array controllers and each other of the N array controllers.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 9, 2010
    Inventors: Rodney A. DeKoning, Charles E. Nichols, William Patrick Delaney, Mohamad El-Batal, Keith Holt
  • Publication number: 20100312963
    Abstract: Disclosed is a storage system architecture. An Environmental service module (ESM) is coupled to one or more array controllers. The ESM is configured with a central processing unit and one or more assist functions. The assist functions may include nonvolatile memory. This nonvolatile memory may be used for write caching, mirroring data, and/or configuration data. The assist functions, or the ESM, may be controlled by the array controllers using SCSI or RDMA commands.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 9, 2010
    Inventors: Rodney A. DeKoning, Bret S. Weber, William Patrick Delaney, Kenneth Day