Abstract: Controlling accesses to target devices such as disk drives by modifying the duty cycle profile of those devices to improve device reliability is disclosed. The utilization of a target device is monitored, and if a device is being overused, that device is given a rest period by reserving it for a special initiator that does not send any commands to the device for a certain period of time. This reduced utilization has the effect of increasing the reliability of the target device. This period of time also adds a delay to the processing of commands for the target device being overutilized so that the device becomes less responsive. This performance penalty creates pressure on system administrators to reduce the number of commands sent to that target device and/or move data to proper devices (that can handle the high number of accesses).

Abstract: A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Abstract: A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: This invention relates to error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: Auto-discrimination between FC and SATA devices upon insertion of a device into a port of a FAST-compatible switch is disclosed. Without user intervention, the port is able to determine the type of device attached, set the appropriate data rate in the Phy or SERDES and, in the case of FC or SATA drives, start the disk insertion process into the active switch zones. The SERDES is first initialized to FC speeds, and the receive path is searched for a receive signal. Upon detecting a receive signal, the detection circuitry then checks to see if a valid SATA Out Of Band (OOB) sequence is received. If a valid SATA OOB sequence is received, the SERDES is configured for SATA speeds and analog settings. If a valid SATA OOB sequence is not received, and instead a FC auto-negotiation process runs to completion, the SERDES remains at FC speeds.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: A switch connection lock and release mechanism is disclosed to prevent out-of-order frames from being received by FC and/or SATA devices. The mechanism includes a set of previous AL_PA registers, alpa_reg[N:0], one for each port, and a bit vector, prev_conn[M:0], one bit for each Buffer Bank (BB). If a connection is closed prematurely, the valid AL_PA of the destination device and the source port number are stored in the previous AL_PA register associated with the destination port, and the bit in the bit vector associated with the source BB is asserted. Together, the valid AL_PA, the source port and the asserted bit form a connection lock on the destination port that effectively will deny access to the destination port to all BBs with the same destination AL_PA and source port number except the source BB.

Abstract: A switch connection lock and release mechanism is disclosed to prevent out-of-order frames from being received by FC and/or SATA devices. The mechanism includes a set of previous AL_PA registers, alpa_reg[N: 0], one for each port, and a bit vector, prev_conn[M:0], one bit for each Buffer Bank (BB). If a connection is closed prematurely, the valid AL_PA of the destination device and the source port number are stored in the previous AL_PA register associated with the destination port, and the bit in the bit vector associated with the source BB is asserted. Together, the valid AL_PA, the source port and the asserted bit form a connection lock on the destination port that effectively will deny access to the destination port to all BBs with the same destination AL_PA and source port number except the source BB.