Patents by Inventor William Patrick Hann

William Patrick Hann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7020140
    Abstract: Receive and transmit blocks for asynchronous transfer mode (ATM) cell delineation are disclosed. The receive block has a plurality of cell delineation blocks, a memory controller, a memory and a bus controller. The transmit block has a bus controller, a plurality of queue selection devices, a plurality of memory queues and a plurality of cell delineation blocks. According to one implementation, the bus controllers receive address mode/select signals and operate to respond to one of a plurality of subsets of port addresses on the ATM physical layer responsive to the address mode/select signals.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: March 28, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: William Patrick Hann, Craig D. Botkin
  • Patent number: 7006520
    Abstract: A system for managing data communication between physical layer devices and ATM layer devices in a cell based ATM network is disclosed. A plurality of low speed physical layer devices a high speed physical layer device are connected to a bus. A bus interface device is coupled to the bus, the low speed physical layer devices, and the high speed physical layer device. The bus interface device is operable to provide equal opportunities to access the bus to any connected physical layer device. An arbiter is coupled to the low speed physical layer devices, the high speed physical layer devices, and the bus interface device. The arbiter is operable to provide the high speed physical layer device with disproportionately frequent access to the bus.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: February 28, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: William Patrick Hann, William Keith Brewer, Matthew Irvin, Richard L. House
  • Patent number: 6965558
    Abstract: A method and system for protecting data transfers between a switch and physical network ports transfers data from a master network interface to a slave network interface, synchronizing the data transfer through a protection first in first out circuit that references the master clock and the slave clock. The master network interface improves ATM switch efficiency by supporting optical trunk and subtend ports for a digital subscriber line access multiplexer. The slave network interface provides back-up protection on a port basis so that a failed trunk port of the master network interface is backed up by the slave network interface even while the master network interface maintains a subtend port.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: November 15, 2005
    Assignee: Cisco Technology, Inc.
    Inventor: William Patrick Hann
  • Patent number: 6535520
    Abstract: A system for managing data communication between physical layer devices and ATM layer devices in a cell based ATM network includes a plurality of low speed physical layer devices, a high speed physical layer device, and a bus connected to the physical layer devices. A bus interface device is coupled to the bus, the low speed physical layer devices, and the high speed physical layer device. The bus interface device permits equal opportunities to access the bus to any connected physical layer device. An arbiter is coupled to the low speed physical layer devices, the high speed physical layer device, and the bus interface device. The arbiter provides the high speed physical layer device with disproportionately frequent access to the bus.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: March 18, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: William Patrick Hann, William Keith Brewer, Matthew Irvin, Richard L. House
  • Patent number: 6381245
    Abstract: A method and apparatus are provided for generating parity for communication between a physical layer device and an ATM layer device is provided. A data bus is monitored for data comprising an ATM cell transmitted from a physical layer device to an ATM layer device. The header error check of the ATM cell is verified and parity for the ATM cell is generated. Parity is provided to the ATM layer device if the header error check is correct.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: April 30, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: William Patrick Hann, Matthew G. Irvin, Richard L. House, William Keith Brewer
  • Patent number: 6269096
    Abstract: Receive and transmit blocks for asynchronous transfer mode (ATM) cell delineation are disclosed. The receive block has a plurality of cell delineation blocks, a memory controller, a memory and a bus controller. The transmit block has a bus controller, a plurality of queue selection devices, a plurality of memory queues and a plurality of cell delineation blocks. According to one implementation, the bus controllers receive address mode/select signals and operate to respond to one of a plurality of subsets of port addresses on the ATM physical layer responsive to the address mode/select signals.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: July 31, 2001
    Assignee: Cisco Technology, Inc.
    Inventors: William Patrick Hann, Craig D. Botkin