Abstract: A design layout is obtained that includes floating fill shapes and signal shapes. Capacitance of the signal shapes is calculated. A simple model is used to calculate a first subset of fill shapes which contribute capacitance to the signal shapes. A capacitance model selected to meet an acceptable error level using minimum computational requirements is then selected from a set of capacitance models. The selected capacitance model is then used to extract the capacitance contribution from the first subset of fill shapes. A second subset of fill shapes is then created based on the extracted capacitance values, and if the estimated capacitance contribution is significant, the capacitance of the second subset extracted using the selected capacitance model. Additional iterations are performed for additional signal shapes.

Abstract: Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.