Patents by Inventor William Patterson
William Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5821885Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: October 13, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5790776Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: June 7, 1995Date of Patent: August 4, 1998Assignee: Tandem Computers IncorporatedInventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, John C. Krause, Kenneth H. Porter, William Joel Watson, Linda Ellen Zalzala
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Patent number: 5768629Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: June 16, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5751932Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Tandem Computers IncorporatedInventors: Robert W. Horst, William Edward Baker, Randall G. Banton, John Michael Brown, William F. Bruckert, William Patterson Bunton, Gary F. Campbell, John Deane Coddington, Richard W. Cutts, Jr., Barry Lee Drexler, Harry Frank Elrod, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Geoffrey I. Iswandhi, Douglas Eugene Jewett, Curtis Willard Jones, Jr., James Stevens Klecka, John C. Krause, Stephen G. Low, Susan Stone Meredith, Steven C. Meyers, David P. Sonnier, William Joel Watson, Patricia L. Whiteside, Frank A. Williams, Linda Ellen Zalzala
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Patent number: 5751955Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Tandem Computers IncorporatedInventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, Daniel L. Fowler, Curtis Willard Jones, Jr., John C. Krause, Michael P. Simpson, William Joel Watson
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Patent number: 5740460Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: April 14, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5677511Abstract: An apparatus directed to portable peripheral cards is disclosed which provides protection against electro-static discharge and electro-magnetic interference. Furthermore, this apparatus provides a solid housing which affords a strong protective structure for the PC board and also protects the ICs housed inside the peripheral card from being easily accessed.Type: GrantFiled: March 20, 1995Date of Patent: October 14, 1997Assignee: National SEmiconductor CorporationInventors: Carl James Taylor, Michael William Patterson
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Patent number: 5675807Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.Type: GrantFiled: June 7, 1995Date of Patent: October 7, 1997Assignee: Tandem Computers IncorporatedInventors: Geoffrey I. Iswandhi, William Edward Baker, William Patterson Bunton, John Deane Coddington, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Susan Stone Meredith, Stephen H. Miller, David Paul Sonnier, William Joel Watson, Frank A. Williams
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Patent number: 5675579Abstract: A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.Type: GrantFiled: June 7, 1995Date of Patent: October 7, 1997Assignee: Tandem Computers IncorporatedInventors: William Joel Watson, William Edward Baker, William F. Bruckert, William Patterson Bunton, David J. Garcia, Robert W. Horst, Geoffrey I. Iswandhi, David Joseph Kinkade, David Paul Sonnier
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Patent number: 4929100Abstract: This invention relates to printing elements for use in a serial wire matrix printer having a plurality of driven wire printing elements. Each printing element has actuating means associated therewith to drive the elements against a ribbon from a retracted position to an actuated position and returned. Each actuating means includes an elongated drive element anchored at opposite ends thereof to piezoelectric crystal stacks. The piezoelectric stacks have electrical supply means for causing expansion of the crystal stacks responsive to an electric signal. The drive element is normally maintained in a taut bowed position and is secured to the piezoelectric crystal stacks so as to be driven toward a straightened condition upon actuation to the piezoelectrical crystal stacks to thereby drive the printing element axially to the printing or actuated position from the retracted position upon actuation of the crystal assembly.Type: GrantFiled: May 4, 1989Date of Patent: May 29, 1990Assignee: International Business Machines Corp.Inventors: William A. Patterson, Dien H. Tong, James R. Wooden
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Patent number: 4768892Abstract: The present invention relates to an assembly of electromagnetic actuators for the hammers of an impact printer arranged side by side and extending along a line. Each actuator comprises a first stator part formed with at least one pole piece, a second stator part formed with at least one pole piece and positioned relative to the first stator part so that the pole pieces are spaced apart so as to form a gap therebetween. A single coil is associated with one of the stator parts. Each actuator also includes an armature member formed with a body of non-magnetizable material, at least one armature element of magnetizable material and a hammer head. The armature member is supported between the stator parts so that the armature element is located adjacent to the gap. Energization of the coil causes the generation of a flux which passes across the gap and through the armature element tending to move the armature element into the gap and to cause the hammer head to move into a print position.Type: GrantFiled: June 26, 1986Date of Patent: September 6, 1988Assignee: International Business Machines CorporationInventors: Douglas S. Brown, William A. Patterson, William D. Thorne
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Patent number: 4421025Abstract: An improved print hammer and actuator mechanism therefor are described. The hammer mechanism comprises a solenoid plunger and push wire or push rod which is directly affixed to one end of the hammer. The opposite end of the hammer is flexibly or pivotably mounted by a spring. The spring is rigidly affixed to the bottom portion of the hammer. It is flexed or twisted to enable the hammer top portion to be deflected. A shock absorbing connector connects the push wire to the print hammer. The position of the solenoid plunger can be adjusted by adjustable abutments at either end of its throw. This adjusts the flight time and the impact force, as well as the relative rest position of the hammer face, since the push wire is firmly connected to both the plunger and to the top of the hammer mechanism. The shock absorbing connector between the end of the push wire and the hammer mechanism controls the amount of force applied at impact.Type: GrantFiled: December 21, 1981Date of Patent: December 20, 1983Assignee: International Business Machines CorporationInventors: William D. Thorne, William A. Patterson