Abstract: A processor includes a plurality of processing elements. The processor is configured to execute a work graph including a plurality of nodes representing kernels executable by one or more processing elements of the plurality of processing elements. A first processing element of the one or more of the processing elements associated with a first node of the plurality of nodes is configured to assign each logical division of a sparse input matrix to a bin of a plurality of bins. Responsive to a dispatch condition associated with a bin of the plurality of bins, the processor is configured to dispatch a workgroup to at least a second processing element associated with at least a second node of the plurality of nodes corresponding to the bin. The workgroup includes a plurality of work items based on one or more logical divisions of the sparse input matrix assigned to the bin.

Abstract: In aspects of near-memory random and pattern-based data generation, a system includes a number generator circuit configured to generate a sequence of numbers, a memory chip configured to store the sequence of numbers, and a memory interface configured to enable communication between the number generator circuit and the memory chip. In one or more implementations, the number generator circuit includes a random number generator circuit configured to generate the sequence of numbers as a sequence of random numbers. Additionally, or alternatively, the number generator circuit includes a pattern fill function configured to generate the sequence of numbers based on a pattern. In other aspects of near-memory random and pattern-based data generation, a memory device includes a base layer, a memory interface, and a number generator circuit interleaved among the base layer and the memory interface.

Abstract: A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.

Abstract: An apparatus and method for efficiently scheduling kernels for execution in a computing system. In various implementations, a computing system includes a cache and a processing circuit with multiple compute circuits and a scheduler. The scheduler groups kernels into scheduling groups where each scheduling group includes particular kernels of the multiple kernels that access a same data set different from a data set of another scheduling group. Each of these scheduling groups is referred to as a “cohort.” The scheduler accesses completion time estimates of kernels of the cohorts. Using the completion time estimates, the number of kernels currently executing, and the number of remaining kernels that have not yet begun execution of each currently scheduled cohort, the scheduler determines whether to immediately schedule a next cohort or delay scheduling the next cohort. By doing so, the scheduler balances throughput and cache contention.

Abstract: A processing unit includes a plurality of processing cores and is configured to arrange a sparse matrix for parallel performance by the cores on different rows of the matrix at least in part by calculating a respective quantity of non-zero elements in each row, assigning each row to a respective collection according to the respective quantity of non-zero elements for the row, wherein the processing unit is configured to assign at least one first row of the sparse matrix to respective collections of in parallel with assigning at least one second row of the sparse matrix to respective collections, and performing at least one mathematical operation on at least a first collection of the plurality of collections in parallel with performing the at least one mathematical operation on at least a second collection of the plurality of collections.

Abstract: A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method can further include completing, by the at least one processor and in response to a determination that the one or more shared resources is available, execution of the one or more processes. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.

Abstract: A technique for scheduling executing items on a highly parallel processing architecture is provided. The technique includes identifying a plurality of execution items that share data, as indicated by having matching commonality metadata; identifying an execution unit for executing the plurality of execution items together; and scheduling the plurality of execution items for execution together on the execution unit.