Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M?1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.