Abstract: A system for limiting access to asset management information is disclosed. According to one embodiment, information is received from a first reporting source about an asset. Information from a second reporting source about the asset is also recited. The information from the first reporting source and the information from the second reporting source is stored in a database such that the information from the first reporting source and the information from the second reporting source can be accessed from the database. A first entity is enabled to access a first subset of the information stored in the database while a second entity is not allowed to access the first subset of the information stored in the database.

Abstract: In a method for automatically directing traffic on a site, information is received regarding a plurality of selected entities on the job site. An indication of a first priority assigned to a first of the plurality of selected entities is received. An indication of a second priority assigned to a second of the plurality of selected entities is received. It is then determined that the first of the plurality of selected entities has a right of way over the second of the plurality of selected entities based upon a comparison of the first priority and the second priority.

Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: In a method for automatically directing traffic on a site, information is received regarding a plurality of selected entities on the job site. An indication of a first priority assigned to a first of the plurality of selected entities is received. An indication of a second priority assigned to a second of the plurality of selected entities is received. It is then determined that the first of the plurality of selected entities has a right of way over the second of the plurality of selected entities based upon a comparison of the first priority and the second priority.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: In a method for automatically directing traffic on a site, information is received regarding a plurality of selected entities on the job site. An indication of a first priority assigned to a first of the plurality of selected entities is received. An indication of a second priority assigned to a second of the plurality of selected entities is received. It is then determined that the first of the plurality of selected entities has a right of way over the second of the plurality of selected entities based upon a comparison of the first priority and the second priority.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M?1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.

Abstract: In a method for automatically directing traffic on a site, information is received regarding a plurality of selected entities on the job site. An indication of a first priority assigned to a first of the plurality of selected entities is received. An indication of a second priority assigned to a second of the plurality of selected entities is received. It is then determined that the first of the plurality of selected entities has a right of way over the second of the plurality of selected entities based upon a comparison of the first priority and the second priority.

Abstract: A system and method for impromptu asset tracking. According to one embodiment, information from a first reporting source about a first asset is received. Asset identification information about a second asset is received from the first reporting source. The first reporting source is coupled with the first asset. The asset identification information comprises identification data gathered by the first reporting source on an impromptu basis when the first reporting source is within a transmission range of a proximity communication device coupled with the second asset. A database is populated with the asset identification information such that the asset identification information can be collected from the database.

Abstract: Streams of data packets and timing pulses are received from a source. Time stamping of the data packets is carried out largely independent of individual timing pulses. A normalised pulse time of arrival is calculated, preferably as a running average over the most recent arrivals. Times of applicability for the content of the packets can then be calculated according to a predetermined relationship between the order of arrival and of corresponding pulses and packets. Data acquisition may take place from an external or internal data source. An example external source is a GPS receiver.

Abstract: A bag suitable for relatively small amounts of products has a front wall and a rear wall, the front wall and rear wall attached through a pair of gusset sidewalls. The bottom of the bag is sealed to provide a base that will support the bag. The top of the bag has a lateral seal which at each end is a seal of the front wall and rear wall to a portion of the gusset sidewall. An end portion of the top lateral seal is removable through a weakened area to open the bag. When opened the upper part of the gusset sidewall is folded outward to form a spout. After product is dispensed form the bag, the gusset sidewall is pushed inward to substantially seal the bag. For subsequent dispensings, the gusset sidewall is pulled outward to open the bag and form the spout and then pushed inward to substantially close the bag.