Abstract: In a digital computer system having a main memory operable at a first speed, a high speed buffer operating at a second speed for temporarily storing selected portions of the main memory, an associative memory for temporarily storing selected main memory addresses and comparing the stored addresses with a newly received address in a read/write operation to generate comparison data, a read only memory a bit configuration reflecting an algorithm, connected to the associative memory for generating a new order of priority for the memory address stored in the associative memory, and a storage unit connected from the read only memory for storing that order of priority for subsequent feedback to the read only memory in a subsequent cycle as a previous order of priority.