Patents by Inventor William Plants
William Plants has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7616508Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.Type: GrantFiled: August 10, 2006Date of Patent: November 10, 2009Assignee: Actel CorporationInventors: Joel Landry, William Plants, Randall Sexton
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Publication number: 20080048717Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Applicant: ACTEL CORPORATIONInventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William Plants
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Publication number: 20080007288Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).Type: ApplicationFiled: September 21, 2007Publication date: January 10, 2008Applicant: ACTEL CORPORATIONInventor: William Plants
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Publication number: 20070189062Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.Type: ApplicationFiled: April 26, 2007Publication date: August 16, 2007Applicant: ACTEL CORPORATIONInventor: William Plants
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Publication number: 20070182600Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.Type: ApplicationFiled: March 20, 2007Publication date: August 9, 2007Applicant: Actel CorporationInventor: William Plants
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Publication number: 20070176631Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: ApplicationFiled: December 7, 2006Publication date: August 2, 2007Applicant: ACTEL CORPORATIONInventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William Plants
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Publication number: 20070103966Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).Type: ApplicationFiled: December 28, 2006Publication date: May 10, 2007Applicant: ACTEL CORPORATIONInventor: William Plants
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Publication number: 20060193181Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.Type: ApplicationFiled: April 24, 2006Publication date: August 31, 2006Inventor: William Plants
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Publication number: 20060145722Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).Type: ApplicationFiled: March 2, 2006Publication date: July 6, 2006Inventor: William Plants
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Publication number: 20060126376Abstract: The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array comprises a configuration memory that has a plurality of configuration bits Read and write circuitry is provided to configure the plurality of configuration bits. A radiation hard latch is coupled to and controls a programmable element and an interface couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the plurality of configuration bits.Type: ApplicationFiled: December 30, 2005Publication date: June 15, 2006Inventor: William Plants
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Publication number: 20060087341Abstract: A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.Type: ApplicationFiled: December 6, 2005Publication date: April 27, 2006Inventors: William Plants, Arunangshu Kundu
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Publication number: 20050257031Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.Type: ApplicationFiled: July 22, 2005Publication date: November 17, 2005Inventors: Arunangshu Kundu, Arnold Goldfein, William Plants, David Hightower
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Publication number: 20050237083Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.Type: ApplicationFiled: May 10, 2004Publication date: October 27, 2005Inventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William Plants
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Publication number: 20050146354Abstract: A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.Type: ApplicationFiled: March 7, 2005Publication date: July 7, 2005Inventors: Arunangshu Kundu, Venkatesh Narayanan, John McCollum, William Plants
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Publication number: 20050081177Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-progamable gate array and the integrated circuit I/O.Type: ApplicationFiled: August 10, 2004Publication date: April 14, 2005Inventors: Samuel Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King Chan, William Plants
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Publication number: 20050040844Abstract: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).Type: ApplicationFiled: September 22, 2004Publication date: February 24, 2005Inventor: William Plants
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Patent number: 5576560Abstract: An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory.Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal.Type: GrantFiled: June 27, 1994Date of Patent: November 19, 1996Assignee: Advanced Micro Devices, Inc.Inventors: Thomas J. Runaldue, William Plants
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Patent number: 5325338Abstract: An integrated circuit memory for a color lookup table for a display system. The memory has a video port and path for reading data identifying colors for pixels at >100 or even >200 MegaHertz, and a CPU port and path for reading and writing data identifying colors at locations in the memory. Each memory cell includes a flip-flop with true and complement terminals. The CPU port includes two pass transistors, each having a first channel terminal coupled to the true or complement terminal, a second channel terminal coupled to a bidirectional bit line of the CPU path, and a gate coupled to a word line of the CPU path. The video port includes an isolated sensing terminal and two transistors. A first transistor has a first channel terminal coupled to the isolated sensing terminal, a second channel terminal coupled to a reference, and a gate coupled to the true or complement terminal.Type: GrantFiled: September 4, 1991Date of Patent: June 28, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Thomas J. Runaldue, William Plants
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Patent number: 4092478Abstract: A dyestuff of the formula: ##STR1## wherein D is the residue of a colored compound of the 6,13-dichlorotriphendioxazine series, the triazine group being attached to a nitrogen atom in D, and wherein:Y is 1 or 2,R.sub.2 is Cl, Br, OH, lower alkoxy, NH.sub.2, a quaternary ammonium group or the residue of a primary or secondary amine,R.sub.1 is H or an alkyl or substituted alkyl group of up to 4 carbon atoms, andR is a hydrocarbon or substituted hydrocarbon radical.The invention provides a range of blue dyestuffs especially useful for reactively dyeing cellulose by heating in the presence of a carbodiimide.Type: GrantFiled: December 21, 1976Date of Patent: May 30, 1978Assignee: Imperial Chemical Industries LimitedInventors: David William Plant, David John Williams