Abstract: An outer packaging bag for use in displaying a retail item. The outer packaging bag includes a peg hole extending therethrough and a perforated line formed therein. The peg hole may be configured to align with an opening defined by a retail item or its packaging that is designed to by removably coupled to a retail display, such that the retail item or its packaging can be removably coupled to the retail display as it is enclosed by the outer packaging bag. The outer packaging bag can be removed from the retail item or retail packaging by pulling the outer packaging bag until it tears away from the retail item or retail packaging at the perforated line formed therein.

Abstract: A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

Abstract: A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.