Patents by Inventor William R. Brown
William R. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11806582Abstract: A tree stand lifting system and method are provided. The system includes a base member, a first strap assembly, and a base pole assembly. The base pole assembly has a first end portion that is rotatably coupled to the base member such that the base pole assembly is rotatable from a first position to a substantially vertical position relative to the base member. The base pole assembly has a first plurality of teeth. The system includes a carriage assembly that is removably coupled to the base pole assembly, and an electric drive unit that is coupled to the carriage assembly. The electric drive unit has a gear assembly and an electric motor. The gear assembly has a main drive gear that rotates and operably engages at least a portion of the first plurality of teeth of the base pole assembly to move the carriage assembly on the base pole assembly.Type: GrantFiled: August 5, 2020Date of Patent: November 7, 2023Assignee: Hytek Innovations LLCInventors: Todd R. Brown, William R. Brown, II
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Publication number: 20230116129Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.Type: ApplicationFiled: December 6, 2022Publication date: April 13, 2023Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
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Patent number: 11532477Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.Type: GrantFiled: July 30, 2018Date of Patent: December 20, 2022Assignee: Micron Technology, Inc.Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
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Patent number: 11189526Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: February 24, 2020Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Patent number: 10811355Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.Type: GrantFiled: November 27, 2018Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20200194305Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Patent number: 10600681Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: October 18, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Patent number: 10522461Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.Type: GrantFiled: July 23, 2018Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventors: Adam L. Olson, Kaveri Jain, Lijing Gou, William R. Brown, Ho Seop Eom, Xue (Gloria) Chen, Anton J. deVilliers
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Patent number: 10388601Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.Type: GrantFiled: December 14, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20190206726Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: ApplicationFiled: October 18, 2018Publication date: July 4, 2019Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Publication number: 20190103350Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.Type: ApplicationFiled: November 27, 2018Publication date: April 4, 2019Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20180366406Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.Type: ApplicationFiled: July 23, 2018Publication date: December 20, 2018Inventors: Adam L. Olson, Kaveri Jain, Lijing Gou, William R. Brown, Ho Seop Eom, Xue (Gloria) Chen, Anton J. deVilliers
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Patent number: 10147638Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.Type: GrantFiled: December 29, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
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Publication number: 20180337035Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
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Patent number: 10049874Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.Type: GrantFiled: October 22, 2015Date of Patent: August 14, 2018Assignee: Micron Technology, Inc.Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
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Patent number: 10032719Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.Type: GrantFiled: May 26, 2017Date of Patent: July 24, 2018Assignee: Micron Technology Inc.Inventors: Adam L. Olson, Kaveri Jain, Lijing Gou, William R. Brown, Ho Seop Eom, Xue (Gloria) Chen, Anton J. deVilliers
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Publication number: 20180114751Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.Type: ApplicationFiled: December 14, 2017Publication date: April 26, 2018Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Patent number: 9911693Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.Type: GrantFiled: August 28, 2015Date of Patent: March 6, 2018Assignee: Micron Technology, Inc.Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
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Publication number: 20170263552Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Adam L. Olson, Kaveri Jain, Lijing Gou, William R. Brown, Ho Seop Eom, Xue (Gloria) Chen, Anton J. deVilliers
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Patent number: 9741580Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.Type: GrantFiled: March 31, 2015Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea