Patents by Inventor William R. Cady

William R. Cady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4432007
    Abstract: An array of electrostatic transducers is fabricated on a monolithic integrated circuit chip having provision for detection, amplification, and signal processing of received echoes. The transducer is multilayered with the form of a parallel plate capacitor, and is made by laterally etching an insulating layer through a small hole in the overlying layer to create a void region, then depositing a sealing layer to seal the etch holes. The upper metallic layers cover the transducer array and other monolithic circuitry and are etched to be interconnections for the various components.
    Type: Grant
    Filed: September 18, 1980
    Date of Patent: February 14, 1984
    Assignee: General Electric Company
    Inventor: William R. Cady
  • Patent number: 4418470
    Abstract: A fabrication technique for monolithic microwave integrated circuits employs silicon-on-sapphire wafers. Active and passive elements are formed together in a series of implant and deposition steps. Electrically isolated islands of semiconductor material are defined upon the substrate. Multiple metallization deposits are employed to simultaneously interconnect the individual circuit elements and form passive elements upon the integrated circuit. The technique allows mass production of integrated circuits with considerable raw material savings.
    Type: Grant
    Filed: October 21, 1981
    Date of Patent: December 6, 1983
    Assignee: General Electric Company
    Inventors: Ronald J. Naster, Simon A. Zaidel, Ying-Chen Hwang, Earl L. Parks, William R. Cady
  • Patent number: 4393578
    Abstract: Junction and metal-semiconductor field effect transistors have a sapphire substrate to realize isolation and reduced capacitance, and have a self-aligned gate to minimize source parasitic resistance. A lightly doped, opposite conductivity type region under the channel forces carriers to flow near the silicon surface where mobility is high; this region is depleted at all times by the P-N junction built-in voltage and acts as an insulator. These devices serve as switches in high speed logic applications and as microwave amplifiers.
    Type: Grant
    Filed: March 22, 1982
    Date of Patent: July 19, 1983
    Assignee: General Electric Company
    Inventors: William R. Cady, SePuan Yu, John R. Eshbach
  • Patent number: 4262399
    Abstract: An array of electrostatic transducers is fabricated on a monolithic integrated circuit chip having provision for detection, amplification, and signal processing of received echoes. The transducer is multilayered with the form of a parallel plate capacitor, and is made by laterally etching an insulating layer through a small hole in the overlying layer to create a void region, then depositing a sealing layer to seal the etch holes. The upper metallic layers cover the transducer array and other monolithic circuitry and are etched to be interconnections for the various components.
    Type: Grant
    Filed: November 8, 1978
    Date of Patent: April 21, 1981
    Assignee: General Electric Co.
    Inventor: William R. Cady