Patents by Inventor William R. Chester

William R. Chester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9300261
    Abstract: A system for driving a plurality of loads each connected to respective signal terminals and to a shared common load terminal. Multiple conventional signal amplifiers each provide a content signal at one of the signal terminals. The signal amplifiers each have a primary-power upper terminal, to receive a first voltage (V1) from a first power supply, and a primary-power lower terminal, to receive a second voltage (V2) from the first power supply. A bias amplifier biases the common load terminal, and has a secondary-power upper terminal to receive a third voltage (V3) from a second power supply and a secondary-power lower terminal to receive a fourth voltage (V4) from the second power supply, wherein V2?V4<V3?V1.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: March 29, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Cary L. Delano, William R. Chester
  • Patent number: 8081785
    Abstract: An audio amplifier system having improved power efficiency by wasting less power in its bias voltage circuit. An amplifier provides a voice signal to a first (+) input of a loudspeaker and a high efficiency converter provides a bias voltage to a second (?) input of the loudspeaker. In multi-loudspeaker systems, a single high efficiency converter can bias all the loudspeakers at a common node. The high efficiency converter can be a charge pump or a buck converter or the like, and has greater than 90% efficiency.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: December 20, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Cary L. Delano, William R. Chester
  • Patent number: 7522433
    Abstract: A voltage reference generation circuit having switch pairs coupled to systematically commutate a flying capacitor among adjacent pairs of voltage rail outputs. The circuit requires only a single flying capacitor, N+1 switch pairs, and N storage capacitors, to generate N intermediate voltage references between VDD and GND. A signal generator produces N+1 non-overlapping switch enable signals to systematically enable the switch pairs and commutate the single flying capacitor between the rail pairs. The flying capacitor remains charged to VDD/(N+1). The N storage capacitors hold their respective reference outputs at VDD*N/(N+1), VDD*(N?1)/(N+1), VDD*(N?2)/(N+1), and so forth.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: April 21, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Cary L. Delano, William R. Chester
  • Publication number: 20080157855
    Abstract: A voltage reference generation circuit having switch pairs coupled to systematically commutate a flying capacitor among adjacent pairs of voltage rail outputs. The circuit requires only a single flying capacitor, N+1 switch pairs, and N storage capacitors, to generate N intermediate voltage references between VDD and GND. A signal generator produces N+1 non-overlapping switch enable signals to systematically enable the switch pairs and commutate the single flying capacitor between the rail pairs. The flying capacitor remains charged to VDD/(N+1). The N storage capacitors hold their respective reference outputs at VDD*N/(N+1), VDD*(N?1)/(N+1), VDD*(N?2)/(N+1), and so forth.
    Type: Application
    Filed: March 20, 2007
    Publication date: July 3, 2008
    Applicant: Leadis Technology, Inc.
    Inventors: Cary L. Delano, William R. Chester