Abstract: The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Two power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

Abstract: The disclosure relates to an input-output multiplexer demultiplexer communication channel which transfers data between a communications controller and a multiplicity of radially attached communications ports. Self-clocking serial bit-synchronous data is transferred on two opposing unidirectional data links between the communications controller and the communications channel. Serial bit-synchronous data is transferred between the communications channel and the communications ports. The communications channel uses one-bit-time response round-robin polling when the communications channel initiates transmissions from the communications ports. Data transmissions from the communications controller are multiplexed on-the-fly in the communications channel to one of the communications ports.

Abstract: The disclosure relates to the use of a flip flop or the like to provide additional protection against the destruction of data located in microprocessor system support circuits.

Abstract: The present disclosure relates to a communications method for communicating data over a data channel that comprises two unidirectional communication lines. A protocol which is set of predetermined control characters is used by the communications method and the protocol is used for transferring data between communicating devices. The communications method combines acknowledgements which are control characters of the protocol transmitted in between messages, piggy-backing which is the combining of control characters of the protocol and data messages, and hold-offs with long time outs which cause the devices to enter a standby idle mode waiting for a responsive control character of the protocol. The communications system and method combines these features so as to permit improved efficient flow control of data information between the communicating devices.

Abstract: The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers control up to 15 line controllers. Each line controller has two ports and each port is connected to a communications controller thereby providing two communications paths to each processor. Redundant power supplies are also used to provide single failure fault-tolerance. A downloadable microprocessor board is provided in combination with, but separate from, an interface board that is designed to meet various communication format specifications and the line controller comprises the two boards.

Abstract: An integrated circuit, slave microprocessor with its bus protocol is described. The slave unit may be activated by either a master microprocessor or a DMA controller. When activated by the DMA controller, handshaking signals between the controller and slave microprocessor permit the transfer of data between these units without intervention by the master microprocessor. Unique flags permit the master processor to readily determine the status of the slave microprocessor.