Patents by Inventor William R. Greer

William R. Greer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102167
    Abstract: A boat used in a chemical vapor deposition (CVD) furnace is configured to hold one or more complex three-dimensional (3D) structures when performing a coating. A platform wafer is placed horizontally in the boat to support the complex 3D structures and a mount is positioned to secure the complex 3D structures on the platform wafer during the CVD process. One or more “witness” wafers may also be placed in the boat for analyzing the thin-film coating. The platform wafer may be positioned between or bracketed by the vertical wafers. Parts with coatings manufactured using LPCVD are further disclosed.
    Type: Application
    Filed: September 28, 2023
    Publication date: March 28, 2024
    Applicant: California Institute of Technology
    Inventors: Matthew R. Dickie, Su C. Chi, Billy Chun-Yip Li, William C. West, Harold Frank Greer
  • Publication number: 20020187119
    Abstract: A single-use toilet deodorizing agent in the form of a solid tablet. The invention is a composition in tablet form made of citric acid, sodium bicarbonate, binding agent, dyes (optional), and a fragrance capable of being released upon dropping the composition in the water. The purpose of the tablet is to be portable and to mask unpleasant odors in the bathroom. The tablet can be deposited or delivered into the toilet water before, during, or after each use.
    Type: Application
    Filed: May 10, 2001
    Publication date: December 12, 2002
    Inventors: William R. Greer, Edward M. Jamison
  • Patent number: 5983025
    Abstract: Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 9, 1999
    Assignee: International Business Machines Corporation
    Inventors: John Edward Derrick, William R. Greer, Christopher Michael Herring
  • Patent number: 5906659
    Abstract: Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: May 25, 1999
    Assignee: International Business Machines Corporation
    Inventors: John Edward Derrick, William R. Greer, Christopher Michael Herring
  • Patent number: 5627993
    Abstract: Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: May 6, 1997
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Abato, William R. Greer, Christopher M. Herring
  • Patent number: 5553265
    Abstract: Methods and system for memory control in a computer system having a store-in cache. In response to main memory read or write requests from a secondary processor, data is transferred into a buffer during a snoop cycle to the store-in cache. The data in the buffer is merged with write-back data from the store-in cache in a write operation. Data is provided directly from the buffer to the secondary processor and to main memory in a read operation. The buffer can be placed on a memory controller of the computer system. A second store-in cache can also be used for main memory transfers.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Abato, William R. Greer, Christopher M. Herring