Abstract: A software development system for generating a software application is provided. The software development system comprises a configuration file generator tool configured to: read a design model comprising a plurality of individual blocks with a specified data flow between the blocks, wherein each block has a defined behavioral expectation, wherein the design model is configured to cause a desired behavior for the software application when given a set of inputs. The configuration file generator tool is further configured to generate a configuration file, based on the design model, that identifies a plurality of preexisting, verified, and compiled/linked software code segments configured to perform mathematical and/or logical actions to cause the desired behavior for the software application.

Abstract: Dual processor accelerated graphics rendering is a method which allows for optimizing graphics performance using two processors and 3D hardware accelerators. This method allows for real time embedded systems to have multiple partitions to render to multiple windows with non-blocking graphics calls. One processor queues up graphics calls within a discrete time because they do not interface with the graphics accelerator hardware. The second processor supports the hardware accelerator with drivers operating in a single partition. This design abstracts the graphics calls from the native interface of the graphics hardware accelerator.

Abstract: In one embodiment of the present invention, a system for displaying images in at least one display window on a display unit includes a display processor configured to generate graphics commands from a received input. A graphics processing unit is coupled to the display processor and includes rendering engine configured to generate graphic data from the graphics commands, an internal memory coupled to the rendering engine, and a general purpose I/O coupled to the rendering engine and configured to transmit messages from the graphics processing unit. A graphics logic device is coupled to the graphics processing unit. The graphics logic device is configured to initiate a transfer of graphic data for an update of a display window from the internal memory to the display unit upon receipt of a message indicative of an available update to the display window.

Abstract: A system for verifying the generation of a critical symbology includes a display processor configured to generate graphic commands from one or more system inputs. The display processor is further configured to determine the critical symbology. A graphics processing unit is coupled to the display processor. The graphics processing unit is configured to generate a plurality of pixels forming an image and is further configured to mark at least a portion of the plurality of pixels to produce marked pixels of the critical symbology. A graphics logic device is coupled to the graphics processing unit and includes an integrity monitoring function and a memory coupled to the integrity monitoring function. The integrity monitoring function is configured to detect the marked pixels and generate data regarding the critical symbology. The memory is configured to store the data regarding the critical symbology.

Abstract: A multi-tiered lookup table is used to progressively map a virtual address to a specific control word that facilitates resolution of the virtual address for a translation lookaside buffer (TLB) miss. In one embodiment, the control word has a compressed and efficiently encoded image of the TLB hardware register data. The control word is accessed with or without a level of indirection in various embodiments. In some embodiments, the control word provides all information needed to decode the majority of memory blocks, or points to a third level for special blocks.

Abstract: High fidelity arcs are produced using a set of interconnected trapezoids, which are transmitted in a highly efficient triangle mesh to a graphics rendering device. Perspective correction capabilities of a graphics engine are used to map a small rectangular texture patch onto the trapezoids, such that the circle appears completely smooth. Anti-aliasing line profiles are applied such that super-sampling is only required in a single dimension.

Abstract: An apparatus and method for providing color dot signals of an image for an active matrix display. The apparatus includes a graphic generator that provides an image input to a graphical processing unit. The graphic generator also control the graphical processing unit to form a plurality of sub-images of the image, where the sub-images represent different color dots of a plurality of pixels of the display. A composite image processor includes a color mask that filters the sub-images based on a predetermined color dot topology of the pixels and interleaves the filtered sub-images to form the color dot signals in appropriate positions in a row of pixels based on the topology. The apparatus provides enhanced resolution as well as permits the use of off shelf components for the graphical processing unit.

Abstract: An apparatus includes a rendering engine to render a foreground of an image. The apparatus also includes a logic, separate from the rendering engine, to merge at least one background color with the foreground of the image.

Abstract: Dual processor accelerated graphics rendering is a method which allows for optimizing graphics performance using two processors and 3D hardware accelerators. This method allows for real time embedded systems to have multiple partitions to render to multiple windows with non-blocking graphics calls. One processor queues up graphics calls within a discrete time because they do not interface with the graphics accelerator hardware. The second processor supports the hardware accelerator with drivers operating in a single partition. This design abstracts the graphics calls from the native interface of the graphics hardware accelerator.

Abstract: A system for verifying the generation of a critical symbology includes a display processor configured to generate graphic commands from one or more system inputs. The display processor is further configured to determine the critical symbology. A graphics processing unit is coupled to the display processor. The graphics processing unit is configured to generate a plurality of pixels forming an image and is further configured to mark at least a portion of the plurality of pixels to produce marked pixels of the critical symbology. A graphics logic device is coupled to the graphics processing unit and includes an integrity monitoring function and a memory coupled to the integrity monitoring function. The integrity monitoring function is configured to detect the marked pixels and generate data regarding the critical symbology. The memory is configured to store the data regarding the critical symbology.

Abstract: In one embodiment of the present invention, a system for displaying images in at least one display window on a display unit includes a display processor configured to generate graphics commands from a received input. A graphics processing unit is coupled to the display processor and includes rendering engine configured to generate graphic data from the graphics commands, an internal memory coupled to the rendering engine, and a general purpose I/O coupled to the rendering engine and configured to transmit messages from the graphics processing unit. A graphics logic device is coupled to the graphics processing unit. The graphics logic device is configured to initiate a transfer of graphic data for an update of a display window from the internal memory to the display unit upon receipt of a message indicative of an available update to the display window.

Abstract: A multi-tiered lookup table is used to progressively map a virtual address to a specific control word that facilitates resolution of the virtual address for a translation lookaside buffer (TLB) miss. In one embodiment, the control word has a compressed and efficiently encoded image of the TLB hardware register data. The control word is accessed with or without a level of indirection in various embodiments. In some embodiments, the control word provides all information needed to decode the majority of memory blocks, or points to a third level for special blocks.

Abstract: A method for generating anti-aliased lines and characters is disclosed. The method comprises generating a texture map based on a distribution and applying the texture map to a polygonal region. In one aspect of this embodiment, the step of generating a texture map based on a distribution further comprises generating a texture map comprising a series of concentric half circles. In the texture map, the concentric half circles represent a decreasing intensity as the radius of the concentric half circle increases. Additionally, in one embodiment, the texture map is generated using a Gaussian distribution. In another aspect of this embodiment, for each texel in a texture map defining a character, the smallest distance between a texel and each line segment that forms a character is calculated. The smallest distance is used to determine an intensity value using the distribution. Then, the texel is associated with the intensity value to form a texture map for the character.

Abstract: A graphics driver and method is provided that facilitates graphics rendering time partitioning to provide improved resource allocation between multiple windows and/or multiple graphics clients. The graphics driver receives high level graphics data from multiple graphics clients and outputs a time-partitioned chain of graphics primitives to the graphics processor. The graphics driver includes a partitioning controller, a graphics translator, and a chain builder. The partitioning controller allocates processing time among the multiple graphics clients, with each of the multiple graphics clients being allocated a periodic budget. The graphics translator translates high level graphics commands received from the graphics clients into graphics primitives that can be processed by the graphics processor. The chain builder creates chains of the graphics primitives that are configured to give each graphics client its associated periodic budget in the graphics processor.

Abstract: A method for generating anti-aliased lines and characters is disclosed. The method comprises generating a texture map based on a distribution and applying the texture map to a polygonal region. In one aspect of this embodiment, the step of generating a texture map based on a distribution further comprises generating a texture map comprising a series of concentric half circles. In the texture map, the concentric half circles represent a decreasing intensity as the radius of the concentric half circle increases. Additionally, in one embodiment, the texture map is generated using a Gaussian distribution. In another aspect of this embodiment, for each texel in a texture map defining a character, the smallest distance between a texel and each line segment that forms a character is calculated. The smallest distance is used to determine an intensity value using the distribution. Then, the texel is associated with the intensity value to form a texture map for the character.

Abstract: An apparatus and method for providing color dot signals of an image for an active matrix display. The apparatus includes a graphic generator that provides an image input to a graphical processing unit. The graphic generator also control the graphical processing unit to form a plurality of sub-images of the image, where the sub-images represent different color dots of a plurality of pixels of the display. A composite image processor includes a color mask that filters the sub-images based on a predetermined color dot topology of the pixels and interleaves the filtered sub-images to form the color dot signals in appropriate positions in a row of pixels based on the topology. The apparatus provides enhanced resolution as well as permits the use of off shelf components for the graphical processing unit.

Abstract: A radar display system (10) according to the present invention generates textured radar display data by utilizing a direct memory access receiver (12) to receive radially scanned radar data, to convert the radially scanned radar data into range bin data sets, and to store the range bin data sets. A graphics renderer (18) stores the set of range bin data sets in a texture memory (20) as a plurality of rectangular textures, and bit maps the rectangular textures to a series of display triangles in a frame buffer (22). The graphics renderer (18) colors the display triangles in accordance with the rectangular textures by performing a bi-linear interpolation of the color and warps the display triangles in accordance with the size of a display (24).

Abstract: A graphics system having a beamformer operating on image data and sub-pixel or fractional address data coming from a modified image memory and graphics processor producing correctly anti-aliased data to be shown on raster displays and in particular on color mosaic active matrix displays.

Abstract: A traffic information display format, situated in a craft, for observing traffic in a volume about the craft, having one or more viewing grids that display traffic on the display in a three-dimensional perspective so that the observer of the display can conceptually and immediately perceive the traffic entities and their statuses, distances, altitudes, ascending rates, descending rates, closing rates, receding rates and other information. The formats are generated by situation and symbol computers and provided to a stroke or flat panel display. The computers follow a system flow design that results in symbol and format generation for a display.

Abstract: A full field memory based stroke written vector occluder consisting of a first full field memory as the primary occlusion mechanism, and a second full field memory as a quantized error correction occlusion function. The apparatus includes a mechanism for generating the address of the second full field memory from the address of the first full field memory added to the least significant bit of the address plus or minus 1. The apparatus also includes an OR gate to provide the real occlusion function which is the result of accessing either or both of the full field memories.