Abstract: A method for establishing signal and power communication between a surgical instrument and a staple cartridge is disclosed.

Abstract: A hand tool and method of use for forming a flange on the end of a vascular graft is disclosed that includes a housing having a handle portion fixed to a trigger portion. A trigger is pivotally fixed within the housing at a lower side of the trigger portion, and includes a finger portion projecting downwardly from the housing. The trigger also includes an actuator portion, connected proximate a pivot that is connected itself to the finger portion. An anvil is pivotally fixed at a first end thereof within and to the trigger portion of the housing. Further, the anvil is slidably fixed at a second end to the actuator portion of the trigger. The anvil has a rigid top surface with a deformation portion thereon. A plurality of mandrels is adapted to laterally engage the deformation portion of the anvil, and each include a spring means for urging the mandrels towards the deformation portion of the anvil.

Abstract: In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.

Abstract: In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.

Abstract: In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post.

Abstract: A thin film reflecting interference filter (RIF) is designed to suppress unwanted harmonics thereby improving the monochromaticity of the radiation. An interference layer of material which has a well-defined plasma oscillation is deposited on a substrate and a mismatch layer is formed thereon. This interference layer exploits the interference between wavefronts reflected from the layer-substrate and the vacuum-layer interfaces to suppress higher order harmonics, while allowing good reflectance at the fundamental wavelength. This is achieved by positioning the RIF in the radiation at an angle of incidence which is greater than the critical angle of the desired fundamental wavelength, but less than critical angles of the harmonics to be suppressed. The mismatch layer increases the reflectance of the unwanted harmonics at the vacuum-layer interface, thus allowing more complete destructive interference of the unwanted harmonics.

Abstract: An interference photocathode includes a reflective substrate and interference layers disposed on said reflective substrate for selectively enhancing a first photoelectric yield of said photocathode when irradiated by radiation having a first wavelength relative to a second photoelectric yield of said photocathode when irradiated by radiation having a second wavelength. In one embodiment, the interference layers include a dielectric layer having a wavelength dependent effective thickness disposed on said reflective substrate such that said effective thickness for radiation having said first wavelength is an odd multiple of a quarter of said first wavelength and said effective thickness for radiation having said second wavelength is an even multiple of a quarter of said second wavelength. In another embodiment, the dielectric layer includes a layer of electrically conductive material and a dielectric material disposed between said layer of electrically conductive material and said reflective substrate.

Abstract: A mirror for reflecting radiation at a desired wavelength in the soft x-ray region, comprises a substrate and a coating on the substrate. The coating contains a first section and a second section. The first section comprises at least one layer made up of at least a spacer sublayer and a nodal sublayer. The optical thickness of each spacer sublayer is selected so that, upon application of the radiation of desired wavelength, the mirror generates a standing wave having a node in the middle of each nodal sublayer. The second section is disposed between the first section and the substrate, and comprises a plurality of optically absorptive layers.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.

Abstract: A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Abstract: A scanning monochromator is disclosed which is capable of operation over a wide bandwidth in an ultra-high vacuum. The monochromator includes a pair of carousel assemblies carrying the optical elements which may be independently positioned translationally along the optical axis of the instrument and also rotationally, which each positioning control operable from outside of the instrument. A carousel on each of the carousel assemblies carries several optical elements and is rotatable to change which optical element is used, also from outside of the instrument.

Abstract: A method for fabricating a semiconductor device of relatively small scale. A conductivity layer is deposited on a substrate of a polarity. Regions of opposite polarity are partially formed on either side of the conductor layer. Vertical layers are formed to partially cover the regions of opposite polarity and are located adjacent to the conductor layer. Extensions of the regions of opposite polarity are formed such that a portion of the extension is defined by the location of the vertical layers.

Abstract: A method for patterning a submicrometer substrate element which is smaller than the reproducible resolution accuracy of optical lithography. A series of layers is deposited upon a top layer pattern using standard methods. An edge of the top layer is positioned at or near where the required submicrometer element is to be patterned. A cavity is formed in one of the intermediate layers by removing that intermediate layer in such a fashion that the layer underneath the edge of the top layer is removed. Next, a conformal layer is deposited upon the structure so that the conformal layer fills the cavity. Then the conformal layer is removed and each of the other layers is sequentially removed in such a fashion that only that portion of the conformal layer that occupied the cavity remains, together with any layers that occupy the space underneath the cavity. The remaining layers are the mask for further patterning.

Abstract: A method of fabricating deep grooves having submicron widths in a semiconductor substrate. A pattern of submicron oxidation masking elements formed on the substrate surface serves as an oxidation mask for a thick oxide layer. After forming the oxide layer, the insulating elements are removed to form a pattern of submicron width openings in the oxide extending to the substrate. A selective anisotropic dry etch is then used to form deep, narrow grooves in the substrate conforming to the pattern of openings which are filled with an insulating material formed by thermal oxidation, chemical vapor deposition, or a combination thereof. This process is used to provide deep dielectric isolation between active areas in high density integrated circuits.

Abstract: A key retaining cylinder for a lock operative on standard keys is disclosed. The cylinder of the lock includes an idler ring driven in rotation, with lost motion, by the lock plug. The idler ring is cooperatively disposed with respect to one of the pins so as to restrict the motion thereof when that lock has been used to lock the lock set and to not restrict the movement thereof when that lock has been used to unlock the lock set. Restricted movement of the pin together with the contrapment of the pin within the combinational notch of the key prevents removal of the key. Further features and embodiments are disclosed including provisions for symmetrical operation thereof for left-handed and right-handed doors.