Patents by Inventor William R. Orso

William R. Orso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6209110
    Abstract: An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: March 27, 2001
    Assignee: Cypress Semiconductor Corporation
    Inventors: Khushrav S. Chhor, William R. Orso
  • Patent number: 6160410
    Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. The insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: December 12, 2000
    Assignee: Cypress Semiconductor Corporation
    Inventors: William R. Orso, Khushrav S. Chhor
  • Patent number: 6057696
    Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: May 2, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventors: William R. Orso, Khushrav S. Chhor, Joseph D. Caliston
  • Patent number: 6018686
    Abstract: An integrated circuit, a programming mechanism and a method are provided for programming manufacturing information upon non-volatile storage devices of the integrated circuit. The storage devices may be programmed after manufacture and prior to assembling the integrated circuit within a semiconductor package. Thereafter, the packaged circuit can be tested to determine where, how and when the integrated circuit was manufactured from among possibly numerous die within a wafer and wafer lot. The storage locations which receive manufacturing indicia are addressed in an address location entirely separate from the addresses which receive data during normal operation of the integrated circuit. Accordingly, manufacturing information is accessible by the manufacturer, and the customer is preferably made unaware of the address space employing those storage locations.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: January 25, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventors: William R. Orso, Craig M. Nishizaki